| Product drift from NBTI: Guardbanding, circuit and statistical effects AT Krishnan, F Cano, C Chancellor, V Reddy, Z Qi, P Jain, J Carulli, ... 2010 International Electron Devices Meeting, 4.3. 1-4.3. 4, 2010 | 42 | 2010 |
| Thermal and IR drop analysis using convolutional encoder-decoder networks VA Chhabria, V Ahuja, A Prabhu, N Patil, P Jain, SS Sapatnekar Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 33 | 2021 |
| New electromigration validation: Via node vector method YJ Park, P Jain, S Krishnan 2010 IEEE International Reliability Physics Symposium, 698-704, 2010 | 30 | 2010 |
| Adjust voltage for thermal mitigation P Jain, M Mehrotra, YC Pan, SHJ Hu US Patent 10,103,714, 2018 | 28 | 2018 |
| Accurate current estimation for interconnect reliability analysis P Jain, A Jain IEEE Transactions on very large scale Integration (VLSI) Systems 20 (9 …, 2011 | 26 | 2011 |
| A systematic approach for analyzing and optimizing cell-internal signal electromigration G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 486-491, 2014 | 24 | 2014 |
| Cell-internal electromigration: Analysis and pin placement based optimization G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 20 | 2015 |
| Technique for aging induced performance drift compensation in an integrated circuit P Jain, HT Mair US Patent 7,689,377, 2010 | 20 | 2010 |
| Judicious choice of waveform parameters and accurate estimation of critical charge for logic SER P Jain, V Zhu Proc. DSN, 2007 | 17 | 2007 |
| Cell-level signal electromigration SS Sapatnekar, V Mishra, P Jain, G Posser, R Reis US Patent 9,665,680, 2017 | 14 | 2017 |
| Method and apparatus for determining electro-migration in integrated circuit designs P Jain, A Mandal US Patent 7,752,582, 2010 | 13 | 2010 |
| Incorporating the role of stress on electromigration in power grids with via arrays V Mishra, P Jain, SK Marella, SS Sapatnekar Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 12 | 2017 |
| Budgeting electromigration-related reliability among metal paths in the design of a circuit P Jain, YJ Park, S Krishnan, GC Prasad US Patent 8,219,953, 2012 | 12 | 2012 |
| SEU reliability analysis of advanced deep-submicron transistors P Jain, J Vasi, RK Lal IEEE Transactions on device and materials reliability 5 (2), 289-295, 2005 | 11 | 2005 |
| Nanotherm: An analytical fourier-boltzmann framework for full chip thermal simulations S Varshney, H Sultan, P Jain, SR Sarangi 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 10 | 2019 |
| Supply voltage tracking clock generator in adaptive clock distribution systems P Jain, KA Bowman, V Bansal US Patent 9,628,089, 2017 | 10 | 2017 |
| A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects P Jain, J Cortadella, SS Sapatnekar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2016 | 10 | 2016 |
| Systems and methods for adaptive clock design P Jain, V Bansal, M Mehrotra, KA Bowman US Patent 9,915,968, 2018 | 9 | 2018 |
| System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems P Jain, V Bansal, R Gulati US Patent 10,089,194, 2018 | 8 | 2018 |
| Stochastic and topologically aware electromigration analysis for clock skew P Jain, SS Sapatnekar, J Cortadella 2015 IEEE International Reliability Physics Symposium, 3D. 4.1-3D. 4.6, 2015 | 8 | 2015 |
Sachin SapatnekarUniversity of MinnesotaVerified email at umn.edu
