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Peng Zheng
Peng Zheng
Intel Corporation, University of California at Berkeley, Georgia Institute of Technology
Verified email at intel.com
Title
Cited by
Cited by
Year
FinFET evolution toward stacked-nanowire FET for CMOS technology scaling
P Zheng, D Connelly, F Ding, TJK Liu
IEEE Transactions on Electron Devices 62 (12), 3945-3950, 2015
632015
Analysis of 7/8-nm bulk-Si FinFET technologies for 6T-SRAM scaling
X Zhang, D Connelly, P Zheng, H Takeuchi, M Hytha, RJ Mears, TJK Liu
IEEE Transactions on Electron Devices 63 (4), 1502-1507, 2016
402016
Simulation-based study of the inserted-oxide FinFET for future low-power system-on-chip applications
P Zheng, D Connelly, F Ding, TJK Liu
IEEE Electron Device Letters 36 (8), 742-744, 2015
382015
Simulation-based study of hybrid fin/planar LDMOS design for FinFET-based system-on-chip technology
YT Wu, F Ding, D Connelly, P Zheng, MH Chiang, JF Chen, TJK Liu
IEEE Transactions on Electron Devices 64 (10), 4193-4199, 2017
282017
Design-technology co-optimization of standard cell libraries on Intel 10nm process
X Wang, R Kumar, SB Prakash, P Zheng, TH Wu, Q Shi, M Nabors, ...
2018 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2018
212018
Variation-aware comparative study of 10-nm GAA versus FinFET 6-T SRAM performance and yield
P Zheng, YB Liao, N Damrongplasit, MH Chiang, TJK Liu
IEEE Transactions on Electron Devices 61 (12), 3949-3954, 2014
192014
Channel stress and ballistic performance advantages of gate-all-around FETs and inserted-oxide FinFETs
D Connelly, P Zheng, TJK Liu
IEEE Transactions on Nanotechnology 16 (2), 209-216, 2017
152017
Advanced MOSFET structures and processes for sub-7 nm CMOS technologies
P Zheng
UC Berkeley, 2016
152016
Inserted-oxide FinFET (iFinFET) design to extend CMOS scaling
P Zheng, D Connelly, F Ding, TJK Liu
2015 International Symposium on VLSI Technology, Systems and Applications, 1-2, 2015
122015
Hydrogenation of graphene nanoribbon edges: Improvement in carrier transport
P Zheng, SE Bryan, Y Yang, R Murali, A Naeemi, JD Meindl
IEEE electron device letters 34 (5), 707-709, 2013
122013
Sub-lithographic patterning via tilted ion implantation for scaling beyond the 7-nm technology node
P Zheng, SW Kim, D Connelly, K Kato, F Ding, L Rubin, TJK Liu
IEEE Transactions on Electron Devices 64 (1), 231-236, 2016
92016
Tilted ion implantation as a cost-efficient sublithographic patterning technique
SW Kim, P Zheng, K Kato, L Rubin, TJ King Liu
Journal of Vacuum Science & Technology B 34 (4), 2016
92016
Enhanced patterning by tilted ion implantation
SW Kim, P Zheng, K Kato, L Rubin, TJK Liu
Alternative Lithographic Technologies VIII 9777, 273-278, 2016
72016
There's still plenty of room at the bottom—And at the Top
TJK Liu, P Zheng, S Kim, K Kato, V Stojanovic
2017 75th Annual Device Research Conference (DRC), 1-2, 2017
42017
Saponins from Panax japonicus alleviate adipose tissue fibrosis and metabolic dysfunction in high-fat-diet-induced obese mice
X Hu, A Sun, H Chen, X Yan, F Ding, P Zheng, Z Li, Y Yan
Biomarkers 27 (8), 784-794, 2022
32022
Cell ratio tuning for high-density SRAM voltage scaling with inserted-oxide FinFETs
F Ding, P Zheng, D Connelly, YT Wu, TJK Liu
IEEE Electron Device Letters 37 (12), 1539-1542, 2016
32016
Benefits of segmented Si/SiGe p-channel MOSFETs for analog/RF applications
N Xu, B Ho, P Zheng, B Wood, V Tran, S Chopra, Y Kim, BY Nguyen, ...
2013 Symposium on VLSI Technology, T142-T143, 2013
32013
Extending the Era of Moore’s Law Through Lower Cost Patterning
P Zheng, L Rubin, TJK Liu
Silicon Semiconductor 39, 32-36, 2017
22017
Sustaining the silicon revolution: From 3-D transistors to 3-D integration
TJK Liu, P Zheng, D Connelly, K Kato, R Nguyen, C Qian, A Peschot
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015
22015
Comparison of 10 nm GAA vs. FinFET 6-T SRAM performance and yield
P Zheng, YB Liao, N Damrongplasit, MH Chiang, WC Hsu, TJK Liu
2014 Silicon Nanoelectronics Workshop (SNW), 1-2, 2014
22014
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