| IncPIRD: Fast learning-based prediction of incremental IR drop CT Ho, AB Kahng 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 43 | 2019 |
| Complementary-FET (CFET) standard cell synthesis framework for design and system technology co-optimization using SMT CK Cheng, CT Ho, D Lee, B Lin, D Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021 | 30 | 2021 |
| SP&R: SMT-based simultaneous Place-and-Route for standard cell synthesis of advanced nodes D Lee, D Park, CT Ho, I Kang, H Kim, S Gao, B Lin, CK Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 23 | 2020 |
| A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT CK Cheng, CT Ho, D Lee, D Park Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 16 | 2020 |
| DTCO acceleration to fight scaling stagnation L Liebmann, D Chanemougame, P Churchill, J Cobb, CT Ho, V Moroz, ... Design-Process-Technology Co-optimization for Manufacturability XIV 11328, 62-76, 2020 | 11 | 2020 |
| Design and system technology co-optimization sensitivity prediction for VLSI technology development using machine learning CK Cheng, CT Ho, C Holtz, B Lin 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2021 | 8 | 2021 |
| Multirow complementary-FET (CFET) standard cell synthesis framework using satisfiability modulo theories (SMTs) CK Cheng, CT Ho, D Lee, B Lin IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …, 2021 | 8 | 2021 |
| ThermPL: Thermal-aware placement based on thermal contribution and locality J Song, YM Lee, CT Ho 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2016 | 6 | 2016 |
| Many-tier vertical gate-all-around nanowire FET standard cell synthesis for advanced technology nodes D Lee, CT Ho, I Kang, S Gao, B Lin, CK Cheng IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …, 2021 | 4 | 2021 |
| InTraSim: Incremental transient simulation of power grids YM Lee, CT Ho IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 4 | 2017 |
| Method and device for recovering data CT Ho, YM Lee US Patent App. 14/474,389, 2015 | 4 | 2015 |
| Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform CK Cheng, CT Ho, D Lee, B Lin IEEE access 10, 65971-65981, 2022 | 3 | 2022 |
| NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model CT Ho, A Ho, M Fojtik, M Kim, S Wei, Y Li, B Khailany, H Ren Proceedings of the 2023 International Symposium on Physical Design, 44-52, 2023 | 2 | 2023 |
| Machine learning prediction for design and system technology co-optimization sensitivity analysis CK Cheng, CT Ho, C Holtz, D Lee, B Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (8 …, 2022 | 2 | 2022 |
| A Parallel-in-Time Circuit Simulator for Power Delivery Networks with Nonlinear Load Models CK Cheng, CT Ho, C Jia, X Wang, Z Zen, X Zha 2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging …, 2020 | 2 | 2020 |
| Net separation-oriented printed circuit board placement via margin maximization CK Cheng, CT Ho, C Holtz 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 288-293, 2022 | 1 | 2022 |
| Novel Computer Aided Design (CAD) Methodology for Emerging Technologies to Fight the Stagnation of Moore’s Law CT Ho University of California, San Diego, 2022 | 1 | 2022 |
| Incremental transient simulation of power grid CT Ho, YM Lee, SH Wei, LC Cheng Proceedings of the 2014 on International symposium on physical design, 93-100, 2014 | 1 | 2014 |
| Novel Transformer Model Based Clustering Method for Standard Cell Design Automation CT Ho, A Chandna, D Guan, A Ho, M Kim, Y Li, H Ren Proceedings of the 2024 International Symposium on Physical Design, 195-203, 2024 | | 2024 |
| Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs SH Wei, YM Lee, CT Ho, CT Sun, LC Cheng 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 1-4, 2013 | | 2013 |
