Hardware implementation aspects of a syndrome-based neural network decoder for bch codes E Kavvousanos, V Paliouras 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2019 | 7 | 2019 |
Simplified Deep-Learning-based decoders for linear block codes E Kavvousanos, V Paliouras, I Kouretas 2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018 | 7 | 2018 |
An iterative approach to syndrome-based deep learning decoding E Kavvousanos, V Paliouras 2020 IEEE Globecom Workshops (GC Wkshps, 1-6, 2020 | 2 | 2020 |
Optimizing deep learning decoders for FPGA implementation E Kavvousanos, V Paliouras 2021 31st International Conference on Field-Programmable Logic and …, 2021 | 1 | 2021 |
A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights E Kavvousanos, I Kouretas, V Paliouras, T Stouraitis 2023 30th IEEE International Conference on Electronics, Circuits and Systems …, 2023 | | 2023 |
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization E Kavvousanos, V Sakellariou, I Kouretas, V Paliouras, T Stouraitis 2023 IEEE 30th Symposium on Computer Arithmetic (ARITH), 102-109, 2023 | | 2023 |
A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation E Kavvousanos, V Paliouras 2022 11th International Conference on Modern Circuits and Systems …, 2022 | | 2022 |