| Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm P Sikka, AR Asati, C Shekhar Microprocessors and Microsystems 80, 103514, 2021 | 21 | 2021 |
| Low‐latency median filter core for hardware implementation of 5× 5 median filtering V Kumar, A Asati, A Gupta IET Image Processing 11 (10), 927-934, 2017 | 21 | 2017 |
| Ultra low power MUX based compressors for wallace and dadda multipliers in sub-threshold regime P Gupta, A Gupta, A Asati American Journal of Engineering and Applied Sciences 8 (4), 702, 2015 | 20 | 2015 |
| Speed optimal FPGA implementation of the encryption algorithms for telecom applications P Sikka, AR Asati, C Shekhar Microprocessors and Microsystems 79, 103324, 2020 | 19 | 2020 |
| Iris localization based on integro-differential operator for unconstrained infrared iris images V Kumar, A Asati, A Gupta 2015 International Conference on Signal Processing, Computing and Control …, 2015 | 18 | 2015 |
| A high-speed, hierarchical 16× 16 array of array multiplier design A Asati 2009 International Multimedia, Signal Processing and Communication …, 2009 | 14 | 2009 |
| Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation V Kumar, A Asati, A Gupta IET Image Processing 12 (10), 1753-1761, 2018 | 13 | 2018 |
| Hardware accelerators for iris localization V Kumar, A Asati, A Gupta Journal of Signal Processing Systems 90, 655-671, 2018 | 12 | 2018 |
| Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images V Kumar, A Asati, A Gupta Engineering Science and Technology, an International Journal 20 (2), 694-704, 2017 | 12 | 2017 |
| Generic modified baugh wooley multiplier A Mukherjee, A Asati 2013 International Conference on Circuits, Power and Computing Technologies …, 2013 | 12 | 2013 |
| High‐speed and area‐efficient Sobel edge detector on field‐programmable gate array for artificial intelligence and machine learning applications P Sikka, AR Asati, C Shekhar Computational Intelligence 37 (3), 1056-1067, 2021 | 11 | 2021 |
| Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications P Sikka, AR Asati, C Shekhar Circuits, Systems, and Signal Processing 40 (6), 2883-2894, 2021 | 10 | 2021 |
| Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images. V Kumar, A Asati, A Gupta International Journal of Electrical & Computer Engineering (2088-8708) 6 (4), 2016 | 10 | 2016 |
| Leakage immune modified pass transistor based 8T SRAM cell in subthreshold Region P Gupta, A Gupta, A Asati International Journal of reconfigurable computing 2015, 6-6, 2016 | 10 | 2016 |
| An iris localization method for noisy infrared iris images V Kumar, A Asati, A Gupta 2015 IEEE International Conference on Signal and Image Processing …, 2015 | 10 | 2015 |
| An improved high speed fully pipelined 500 MHz 8× 8 Baugh Wooley multiplier design using 0.6 μm CMOS TSPC logic design style A Asati 2008 IEEE Region 10 and the Third international Conference on Industrial and …, 2008 | 10 | 2008 |
| A novel redundant binary number to natural binary number converter SK Sahoo, A Gupta, AR Asati, C Shekhar Journal of Signal Processing Systems 59, 297-307, 2010 | 9 | 2010 |
| RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications P Sikka, AR Asati, C Shekhar Journal of Ambient Intelligence and Humanized Computing 12 (7), 7273-7279, 2021 | 7 | 2021 |
| Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm A Gupta, P Gupta, A Asati International Journal of Electronics 105 (8), 1399-1415, 2018 | 7 | 2018 |
| Iris based biometric identification system A Kumar, AR Asati 2014 International Conference on Audio, Language and Image Processing, 260-265, 2014 | 7 | 2014 |
Anu GuptaBITS, PILANIVerified email at pilani.bits-pilani.ac.in
