| 2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure S Kumar, E Goel, K Singh, B Singh, PK Singh, K Baral, S Jit IEEE Transactions on Electron Devices 64 (3), 960-968, 2017 | 167 | 2017 |
| 2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure S Kumar, K Singh, S Chander, E Goel, PK Singh, K Baral, B Singh, S Jit IEEE Transactions on Electron Devices 65 (1), 331-338, 2017 | 69 | 2017 |
| Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis PK Singh, K Baral, S Kumar, S Chander, MR Tripathy, AK Singh, S Jit Applied Physics A 126, 1-11, 2020 | 17 | 2020 |
| Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge PK Singh, K Baral, S Kumar, S Chander, S Jit Indian Journal of physics 94, 841-849, 2020 | 11 | 2020 |
| 2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET K Baral, PK Singh, S Kumar, A Singh, M Tripathy, S Chander, S Jit AEU-International Journal of Electronics and Communications 116, 153071, 2020 | 11 | 2020 |
| Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability K Baral, PK Singh, S Kumar, S Chander, S Jit Superlattices and Microstructures 138, 106364, 2020 | 9 | 2020 |
| Impact of Strain on Electrical Characteristic of Double-Gate TFETs with a SiO2/RfO2Stacked Gate-Oxide Structure PK Singh, S Kumar, S Chander, K Baral, S Jit 2017 14th IEEE India Council International Conference (INDICON), 1-5, 2017 | 8 | 2017 |
| 2-D analytical model for electrical characteristics of dual metal heterogeneous gate dielectric double-gate TFETs with localized interface charges S Kumar, K Singh, K Baral, PK Singh, S Jit Silicon 13, 2519-2527, 2021 | 7 | 2021 |
| Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs PK Singh, K Baral, S Kumar, MR Tripathy, AK Singh, RK Upadhyay, ... Silicon 13, 1731-1739, 2021 | 5 | 2021 |
| Impact of Gate Dielectrics on Analog/RF Performance of Double Gate Tunnel Field Effect Transistor PK Singh, K Baral, S Chander, S Kumar, MR Tripathy, AK Singh, S Jit 2019 3rd International Conference on Electronics, Materials Engineering …, 2019 | 5 | 2019 |
| Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis K Baral, PK Singh, G Kumar, AK Singh, MR Tripathy, S Kumar, S Jit Materials Science in Semiconductor Processing 133, 105966, 2021 | 2 | 2021 |
| Influence of Temperature on Analog/Radio Frequency Appearances of Heterojunction Cylindrical Gate Tunnel FETs PK Singh, K Baral, AK Singh, MR Tripathy, RK Upadhyay, AP Singh, S Jit 2020 IEEE International Conference on Computing, Power and Communication …, 2020 | 2 | 2020 |
| A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes K Baral, PK Singh, S Kumar, MR Tripathy, AK Singh, S Chander, S Jit Semiconductor Science and Technology 35 (8), 085014, 2020 | 2 | 2020 |
| Subthreshold swing modeling of gaussian doped double-gate MOSFETs and its validation based on TCAD simulation PK Singh, K Baral, S Kumar, AK Singh, MR Tripathy, RK Upadhyay, S Jit 2020 IEEE International Conference on Electronics, Computing and …, 2020 | 1 | 2020 |
| A unified 2-D model for nanowire junctionless accumulation and inversion mode MOSFET in quasi-ballistic regime K Baral, PK Singh, S Kumar, AK Singh, DK Jarwal, S Jit Solid-State Electronics 193, 108282, 2022 | | 2022 |
| Communications (AEÜ) K Baral, PK Singh, S Kumar, A Singh, M Tripathy, S Chander, S Jit | | 2020 |
