| Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator G Abich, R Garibotti, V Bandeira, F da Rosa, J Gava, F Bortolon, ... IET Computers & Digital Techniques 15 (2), 125-142, 2021 | 14 | 2021 |
| Evaluation of compiler optimization flags effects on soft error resiliency GE Medeiros, FT Bortolon, R Reis, L Ost 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2018 | 13 | 2018 |
| Exploring the impact of soft errors on NoC-based multiprocessor systems FT Bortolon, G Abich, S Bampi, R Reis, F Moraes, L Ost 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 5 | 2018 |
| Estimation methods for static noise margins in CMOS subthreshold logic circuits FT Bortolon, FG Moraes, MT Moreira, S Bampi Proceedings of the 30th Symposium on Integrated Circuits and Systems Design …, 2017 | 2 | 2017 |
| Static noise margin analysis for CMOS logic cells in near-threshold FT Bortolon | 1 | 2018 |
| Hardware and software infrastructure to implement many-core systems in modern FPGAs FT Bortolon, FG Moraes Proceedings of the 30th Symposium on Integrated Circuits and Systems Design …, 2017 | 1 | 2017 |
| Design and analysis of the HF-RISC processor targeting voltage scaling applications FT Bortolon, S Johann Filho, M Gibiluka, S Bampi, NLV Calazans, ... 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2016 | 1 | 2016 |
| An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs C Marcon, A Amory, T Webber, FT Bortolon, T Volpato, J Munareto 2013 International Symposium on Rapid System Prototyping (RSP), 24-29, 2013 | | 2013 |
| DEVELOPMENT OF MPSOCS MANAGEMENT SYSTEMS IN MODERN FPGAS FT Bortolon, FG Moraes | | |
Fernando Gehm MoraesProfessor at the School of Technology at PUCRSVerified email at pucrs.br
