| Hardware/software co-compilation with the Nymble system J Huthmann, B Liebig, J Oppermann, A Koch 2013 8th International Workshop on Reconfigurable and Communication-Centric …, 2013 | 41 | 2013 |
| Automatic mapping of the sum-product network inference problem to fpga-based accelerators L Sommer, J Oppermann, A Molina, C Binnig, K Kersting, A Koch 2018 IEEE 36th International Conference on Computer Design (ICCD), 350-357, 2018 | 30 | 2018 |
| ILP-based modulo scheduling for high-level synthesis J Oppermann, A Koch, M Reuter-Oppermann, O Sinnen Proceedings of the International Conference on Compilers, Architectures and …, 2016 | 26 | 2016 |
| Noftl-kv: Tackling write-amplification on kv-stores with native storage management T Vinçon, S Hardock, C Riegger, J Oppermann, A Koch, I Petrov Advances in database technology-EDBT 2018: 21st International Conference on …, 2018 | 22 | 2018 |
| Design-space exploration with multi-objective resource-aware modulo scheduling J Oppermann, P Sittel, M Kumm, M Reuter-Oppermann, A Koch, O Sinnen European Conference on Parallel Processing, 170-183, 2019 | 15 | 2019 |
| ILP-based modulo scheduling and binding for register minimization P Sittel, M Kumm, J Oppermann, K Möller, P Zipf, A Koch 2018 28th International Conference on Field Programmable Logic and …, 2018 | 15 | 2018 |
| Automatic high-level synthesis of multi-threaded hardware accelerators J Huthmann, J Oppermann, A Koch 2014 24th International Conference on Field Programmable Logic and …, 2014 | 15 | 2014 |
| Resource-efficient logarithmic number scale arithmetic for SPN inference on FPGAs L Weber, L Sommer, J Oppermann, A Molina, K Kersting, A Koch 2019 International Conference on Field-Programmable Technology (ICFPT), 251-254, 2019 | 13 | 2019 |
| Exact and practical modulo scheduling for high-level synthesis J Oppermann, M Reuter-Oppermann, L Sommer, A Koch, O Sinnen ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12 (2), 1-26, 2019 | 10 | 2019 |
| HatScheT: A Contribution to Agile HLS P Sittel, J Oppermann, M Kumm, A Koch, P Zipf FSP Workshop 2018; Fifth International Workshop on FPGAs for Software …, 2018 | 10 | 2018 |
| Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators J Oppermann, A Koch, T Yu, O Sinnen 2015 25th International Conference on Field Programmable Logic and …, 2015 | 7 | 2015 |
| Synthesis of interleaved multithreaded accelerators from OpenMP loops L Sommer, J Oppermann, J Hofmann, A Koch 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 6 | 2017 |
| Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models T Yu, J Oppermann, C Bradley, O Sinnen Concurrency and Computation: Practice and Experience 28 (5), 1480-1506, 2016 | 6 | 2016 |
| SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis J Oppermann, L Sommer, L Weber, M Reuter-Oppermann, A Koch, ... 2019 International Conference on Field-Programmable Technology (ICFPT), 36-44, 2019 | 4 | 2019 |
| Dependence graph preprocessing for faster exact modulo scheduling in high-level synthesis J Oppermann, M Reuter-Oppermann, L Sommer, O Sinnen, A Koch 2018 28th International Conference on Field Programmable Logic and …, 2018 | 4 | 2018 |
| Automatic synthesis of fpga-based accelerators for the sum-product network inference problem L Sommer, J Oppermann, A Molina, C Binnig, K Kersting, A Koch ICML 2018 Workshop on Tractable Probabilistic Models (TPM), 2018 | 4 | 2018 |
| Detecting kernels suitable for C-based high-level hardware synthesis J Oppermann, A Koch 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, Advanced …, 2016 | 4 | 2016 |
| SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors M Damian, J Oppermann, C Spang, A Koch Proceedings of the 59th ACM/IEEE Design Automation Conference, 169-174, 2022 | 3 | 2022 |
| GeMS: a generator for modulo scheduling problems: work in progress J Oppermann, S Vollbrecht, M Reuter-Oppermann, O Sinnen, A Koch Proceedings of the International Conference on Compilers, Architecture and …, 2018 | 3 | 2018 |
| The Scale4Edge RISC-V Ecosystem W Ecker, P Adelt, W Mueller, R Heckmann, M Krstic, V Herdt, R Drechsler, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 808-813, 2022 | 2 | 2022 |
Oliver SinnenParallel and Reconfigurable Computing Lab, University of AucklandVerified email at auckland.ac.nz
