| Understanding the threshold voltage instability during OFF-state stress in p-GaN HEMTs L Efthymiou, K Murukesan, G Longobardi, F Udrea, A Shibib, K Terrill IEEE Electron Device Letters 40 (8), 1253-1256, 2019 | 94 | 2019 |
| Gate stress induced threshold voltage instability and its significance for reliable threshold voltage measurement in p-GaN HEMT K Murukesan, L Efthymiou, F Udrea 2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA …, 2019 | 20 | 2019 |
| POCl3diffusion process optimization for the formation of emitters in the crystalline silicon solar cells K Murukesan, S Kumbhar, AK Kapoor, A Dhaul, S Saravanan, R Pinto, ... 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), 3011-3013, 2014 | 15 | 2014 |
| High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device K Murukesan, WC Chiang, CL Tsai, KH Huo, KM Wu, PC Chen, RY Su, ... US Patent 10,535,730, 2020 | 12 | 2020 |
| High Voltage Semiconductor Device Karthick Murukesan, Yi-Cheng Chiu, H.C.Lin, Yi-Men Chen, Chen-Chien Chen ... US Patent 9,680,009, 2017 | 12* | 2017 |
| On the challenges of reliable threshold voltage measurement in Ohmic and Schottky gate p-GaN HEMTs K Murukesan, L Efthymiou, F Udrea IEEE Journal of the Electron Devices Society 9, 831-838, 2021 | 11 | 2021 |
| Towards fabrication of low cost high efficiency c-Si solar cells: Progress and optimization using TCAD simulation study K Murukesan, NR Mavilla 2012 38th IEEE Photovoltaic Specialists Conference, 002218-002222, 2012 | 6 | 2012 |
| An investigation of silicon boride surface layer resulting from boron diffusion in silicon K Murukesan, DVS Rao, K Muraleedharan, AK Kapoor, A Dhaul, ... 2012 38th IEEE Photovoltaic Specialists Conference, 000278-000281, 2012 | 3 | 2012 |
| High voltage resistor device C Yi-Cheng, WC Chiang, CL Tsai, KM Wu, SJ Lin, C Yi-Min, HC Lin, ... US Patent App. 16/199,483, 2019 | 2 | 2019 |
| Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device K Murukesan, WC Chiang, CH Chung, CL Tsai, KM Wu, SJ Lin, TS Lin, ... US Patent 10,679,987, 2020 | 1 | 2020 |
| Semiconductor device structure with high voltage device HC Lin, C Yi-Cheng, K Murukesan, C Yi-Min, SJ Lin, WC Chiang, ... US Patent 11,942,543, 2024 | | 2024 |
| High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device K Murukesan, WC Chiang, CL Tsai, KH Huo, KM Wu, PC Chen, RY Su, ... US Patent 11,862,675, 2024 | | 2024 |
| Semiconductor device structure with high voltage device HC Lin, C Yi-Cheng, K Murukesan, C Yi-Min, SJ Lin, WC Chiang, ... US Patent 11,424,359, 2022 | | 2022 |
| Semiconductor device structure with high voltage device HC Lin, C Yi-Cheng, K Murukesan, C Yi-Min, SJ Lin, WC Chiang, ... US Patent 10,892,360, 2021 | | 2021 |
| Estimation of Phosphorus Concentration in Silicon Thin Film on Glass Using ToF-SIMS MA Hossion, K Murukesan, BM Arora Mass Spectrometry Letters 12 (2), 47-52, 2021 | | 2021 |
| High voltage resistor device Yi-Cheng CHIU, WC Chiang, CL Tsai, KM Wu, SJ Lin, Yi-Min CHEN, ... US Patent 20190006460A1, 2019 | | 2019 |
| Novel EPI layer to prevent detrimental Boron autodoping effect in UHV device Yi-Cheng Chiu, Karthick Murukesan, H.C.Lin, Chen Chien Chang TW Patent Trade Secret (R) TSMC,Taiwa n, 2015 | | 2015 |
| Effect of the front pyramid heights on the performance of the inline diffused screen printed monocrystalline silicon solar cells MBB Prabir k. Basu, karthick Murukesan, Debajyothi PV Asia pacific conference 2012, 129, 2012 | | 2012 |
Loizos EfthymiouUniversity of CambridgeVerified email at cam.ac.uk
