| Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design YT Chen, J Cong, H Huang, B Liu, C Liu, M Potkonjak, G Reinman Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, 45-50, 2012 | 104 | 2012 |
| When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration YT Chen, J Cong, Z Fang, J Lei, P Wei 8th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 16), 2016 | 101 | 2016 |
| A Novel High-Throughput Acceleration Engine for Read Alignment YT Chen, J Cong, J Lei, P Wei International Symposium on Field-Programmable Custom Computing Machines …, 2015 | 65 | 2015 |
| The SMEM Seeding Acceleration for DNA Sequence Alignment MCF Chang, YT Chen, J Cong, PT Huang, CL Kuo, CH Yu Field-Programmable Custom Computing Machines (FCCM), 2016 IEEE 24th Annual …, 2016 | 60 | 2016 |
| Static and dynamic co-optimizations for blocks mapping in hybrid caches YT Chen, J Cong, H Huang, C Liu, R Prabhakar, G Reinman Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 54 | 2012 |
| Accelerator-rich CMPs: From concept to real hardware YT Chen, J Cong, MA Ghodrat, M Huang, C Liu, B Xiao, Y Zou Computer Design (ICCD), 2013 IEEE 31st International Conference on, 169-176, 2013 | 43 | 2013 |
| Fine-grained sleep transistor sizing algorithm for leakage power minimization DS Chiou, DC Juan, YT Chen, SC Chang Design Automation Conference, 2007. DAC'07. 44th ACM/IEEE, 81-86, 2007 | 37 | 2007 |
| Functional Isolation of Tumor-Initiating Cells using Microfluidic-Based Migration Identifies Phosphatidylserine Decarboxylase as a Key Regulator YC Chen, B Humphries, R Brien, AE Gibbons, YT Chen, T Qyli, HR Haley, ... Scientific Reports 8 (1), 1-13, 2018 | 36 | 2018 |
| An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon YT Chen, DC Juan, MC Lee, SC Chang Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference …, 2007 | 34 | 2007 |
| An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs DC Juan, YT Chen, MC Lee, SC Chang Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18 (2 …, 2010 | 31 | 2010 |
| HC-Sim: A fast and exact L1 cache simulator with scratchpad memory co-simulation support YT Chen, J Cong, G Reinman Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2011 …, 2011 | 20 | 2011 |
| DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters YL Lee, DC Juan, XA Tseng, YT Chen, SC Chang Joint European Conference on Machine Learning and Knowledge Discovery in …, 2017 | 17 | 2017 |
| CS-BWAMEM: A fast and scalable read aligner at the cloud scale for whole genome sequencing YT Chen, J Cong, S Li, M Peto, P Spellman, P Wei, P Zhou High Throughput Sequencing Algorithms and Applications (HiTSeq), Poster Session, 2015 | 16 | 2015 |
| Sleep transistor sizing in power gating designs DS Chiou, YT Chen, DC Juan, SC Chang ASIC, 2007. ASICON'07. 7th International Conference on, 1326-1331, 2007 | 11 | 2007 |
| Sleep transistor sizing for leakage power minimization considering temporal correlation DS Chiou, YT Chen, DC Juan, SC Chang Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2010 | 10 | 2010 |
| ARACompiler: A Prototyping Flow and Evaluation Framework for Accelerator-Rich Architectures YT Chen, J Cong, B Xiao International Symposium on Performance Analysis of Systems and Software, 157-158, 2015 | 9 | 2015 |
| An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs MC Lee, YT Chen, YT Cheng, SC Chang Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 9 | 2009 |
| Customizable Computing YT Chen, J Cong, M Gill, G Reinman, B Xiao Synthesis Lectures on Computer Architecture 10 (3), 1-118, 2015 | 7 | 2015 |
| ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture YT Chen, J Cong, Z Fang, P Zhou Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 6 | 2016 |
| Interconnect synthesis of heterogeneous accelerators in a shared memory architecture YT Chen, J Cong Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International …, 2015 | 6 | 2015 |
