| Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness P Poliakov, P Blomme, MM Corbalan, J Van Houdt, W Dehaene Microelectronics Reliability 51 (5), 919-924, 2011 | 32 | 2011 |
| Variability aware modeling of SoCs: From device variations to manufactured system yield M Miranda, B Dierickx, P Zuber, P Dobrovoln, F Kutscherauer, P Roussel, ... 2009 10th International Symposium on Quality Electronic Design, 547-553, 2009 | 23 | 2009 |
| Linking EUV lithography line edge roughness and 16 nm NAND memory performance AV Pret, P Poliakov, R Gronheid, P Blomme, MM Corbalan, W Dehaene, ... Microelectronic Engineering 98, 24-28, 2012 | 19 | 2012 |
| Induced Variability of Cell-to-Cell Interference by Line Edge Roughness in nand Flash Arrays P Poliakov, P Blomme, AV Pret, MM Corbalan, R Gronheid, D Verkest, ... Electron Device Letters, IEEE 33 (2), 164-166, 2012 | 12 | 2012 |
| Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories P Poliakov, P Blomme, AV Pret, MM Corbalan, R Gronheid, D Verkest, ... Microelectronics Reliability 52 (3), 525-529, 2012 | 5 | 2012 |
| Impact of line edge roughness on cell-to-cell coupling variability in NAND flash arrays P Poliakov, P Blomme, M Miranda Corbalan, A Anchlia, P Dobrovolny, ... | 3 | 2010 |
| Circuit design for bias compatibility in novel FinFET-based floating-body RAM P Poliakov, A Anchlia, MG Bardon, B Rooseleer, B De Wachter, N Collaert, ... IEEE Transactions on Circuits and Systems II: Express Briefs 57 (3), 183-187, 2010 | 2 | 2010 |
| Spacer-Defined EUV Lithography Reducing Variability of 12nm NAND Flash Memories P Poliakov, P. Blomme, AV Pret, MM Corbalan, R Gronheid, V Wiaux, ... Memory Workshop (IMW), 2012 4th IEEE International, 1 - 4, 0 | 2* | |
| Bridging lithography processes with NAND flash ECC complexity P Poliakov, P Blomme, AV Pret, MM Corbalan, J Van Houdt, W Dehaene 2011 3rd IEEE International Memory Workshop (IMW), 1-4, 2011 | 1 | 2011 |
| Trades-off between line edge roughness and error-correcting codes requirements for NAND Flash Memories P Poliakov, P Blomme, A Vaglio Pret, M Miranda Corbalan, R Gronheid, ... | | 2012 |
| Modeling and exploration of novel non-volatile memory technologies P Poliakov | | 2012 |
| Impact of EUV lithography line edge roughness on 16 nm memory generation A Vaglio Pret, P Poliakov, D Bianchi, R Gronheid, P Blomme, ... | | 2011 |
| Roughness analysis for (EUV) optical lithography A Vaglio Pret, P Poliakov, D Bianche, R Gronheid, P Blomme, ... | | 2010 |
| TH Wang, C.-H. Tsai and Y.-S. Lai Effect of the combination of surface finishes and solder balls on JEDEC drop reliability of chip-scale packages DA Aldemir, A Kökce, AF Özdemir, S Joo, H Liang, Y Zhao, S He, AV Pret, ... | | |
Davide Bianchi, PhDSoftware Developer, IMS Nanofabrication GmbHVerified email at ims.co.at
