| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 772 | 2017 |
| FinFET design considerations based on 3-D simulation and analytical modeling G Pei, J Kedzierski, P Oldiges, M Ieong, ECC Kan IEEE Transactions on Electron Devices 49 (8), 1411-1419, 2002 | 363 | 2002 |
| Low-energy proton-induced single-event-upsets in 65 nm node, silicon-on-insulator, latches and memory cells KP Rodbell, DF Heidel, HHK Tang, MS Gordon, P Oldiges, CE Murray IEEE Transactions on Nuclear Science 54 (6), 2474-2479, 2007 | 201 | 2007 |
| Modeling line edge roughness effects in sub 100 nanometer gate length devices P Oldiges, Q Lin, K Petrillo, M Sanchez, M Ieong, M Hargrove 2000 International Conference on Simulation Semiconductor Processes and …, 2000 | 201 | 2000 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 175 | 2016 |
| Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond SD Kim, M Guillorn, I Lauer, P Oldiges, T Hook, MH Na 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015 | 126 | 2015 |
| Strained Si CMOS (SS CMOS) technology: opportunities and challenges K Rim, R Anderson, D Boyd, F Cardone, K Chan, H Chen, S Christansen, ... Solid-State Electronics 47 (7), 1133-1139, 2003 | 121 | 2003 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 108 | 2014 |
| Channel doping impact on FinFETs for 22nm and beyond CH Lin, R Kambhampati, RJ Miller, TB Hook, A Bryant, W Haensch, ... 2012 Symposium on VLSI Technology (VLSIT), 15-16, 2012 | 85 | 2012 |
| 2-D MOSFET modeling including surface effects and impact ionization by self-consistent solution of the Boltzmann, Poisson, and hole-continuity equations W Liang, N Goldsman, I Mayergoyz, PJ Oldiges IEEE Transactions on Electron Devices 44 (2), 257-267, 1997 | 85 | 1997 |
| Sub-25nm FinFET with advanced fin formation and short channel effect engineering T Yamashita, VS Basker, T Standaert, CC Yeh, T Yamamoto, K Maitra, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 14-15, 2011 | 77 | 2011 |
| Challenges and opportunities for high performance 32 nm CMOS technology JW Sleight, I Lauer, O Dokumaci, DM Fried, D Guo, B Haran, S Narasimha, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 67 | 2006 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 65 | 2016 |
| Alpha-particle-induced upsets in advanced CMOS circuits and technology DF Heidel, KP Rodbell, EH Cannon, C Cabral, MS Gordon, P Oldiges, ... IBM Journal of Research and Development 52 (3), 225-232, 2008 | 59 | 2008 |
| Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells DF Heidel, KP Rodbell, P Oldiges, MS Gordon, HHK Tang, EH Cannon, ... IEEE transactions on nuclear science 53 (6), 3512-3517, 2006 | 57 | 2006 |
| Multi-bit upsets in 65nm SOI SRAMs EH Cannon, MS Gordon, DF Heidel, AJ KleinOsowski, P Oldiges, ... 2008 IEEE International Reliability Physics Symposium, 195-201, 2008 | 39 | 2008 |
| Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond CH Lin, W Haensch, P Oldiges, H Wang, R Williams, J Chang, M Guillorn, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 16-17, 2011 | 38 | 2011 |
| Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices AJ KleinOsowski, P Oldiges, RQ Williams, PM Solomon IEEE Transactions on Nuclear Science 53 (6), 3321-3328, 2006 | 38 | 2006 |
| Theoretical determination of the temporal and spatial structure of/spl alpha/-particle induced electron-hole pair generation in silicon P Oldiges, R Dennard, D Heidel, B Klaasen, F Assaderaghi, M Ieong IEEE Transactions on Nuclear Science 47 (6), 2575-2579, 2000 | 36 | 2000 |
| Bottom oxidation through STI (BOTS)—A novel approach to fabricate dielectric isolated FinFETs on bulk substrates K Cheng, S Seo, J Faltermeier, D Lu, T Standaert, I Ok, A Khakifirooz, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 35 | 2014 |
