MOBA: multi objective bat algorithm for combinatorial optimization in VLSI LL Laudis, S Shyam, C Jemila, V Suresh Procedia Computer Science 125, 840-846, 2018 | 25 | 2018 |
An adaptive symbiosis based metaheuristics for combinatorial optimization in VLSI LL Laudis, N Ramadass, S Shyam, R Benschwartz, V Suresh Procedia Computer Science 167, 205-212, 2020 | 7 | 2020 |
A study: Various NP-hard problems in VLSI and the need for biologically inspired heuristics LL Laudis, S Shyam, V Suresh, A Kumar Recent Findings in Intelligent Computing Techniques: Proceedings of the 5th …, 2018 | 5 | 2018 |
Modified SA algorithm for wirelength minimization in VLSI circuits LL Laudis, S Anand, AK Sinha 2015 International Conference on Circuits, Power and Computing Technologies …, 2015 | 4 | 2015 |
A Lion’s pride inspired algorithm for VLSI floorplanning LL Laudis, N Ramadass Journal of Circuits, Systems and Computers 29 (01), 2050003, 2020 | 3 | 2020 |
Metaheuristic approach for VLSI 3D-Floorplanning LL Laudis, AK Sinha Int. J. Sci. Res 2 (18), 202-203, 2013 | 2 | 2013 |
AADHAR License Management (ALM) System in India Using AADHAR IDs LL Laudis, PD Saravanan, S Anand, AK Sinha Proceedings of the International Conference on Soft Computing Systems: ICSCS …, 2016 | 1 | 2016 |
FPGA implementaion: Smart card based license management using iris scanning approach LL Laudis, AK Sinha, PD Saravanan, S Anand 2014 International Conference on Science Engineering and Management Research …, 2014 | 1 | 2014 |
A study of various multi objective techniques in simulated annealing LL Laudis Int. J. Eng. Res. Technol.(ESRSA Publications) 3 (2), 2014 | 1 | 2014 |
Symbiotic Organisms Search (SOS) algorithm based on B* tree Crossover for fixed outline VLSI floorplans M Shunmugathammal, VK Sundari, LL Laudis 2021 International Conference on System, Computation, Automation and …, 2021 | | 2021 |
Murderer Algorithm Based Automatic Waking up System LL Laudis, AK Sinha International Journal of Scientific and Research Publications, 7, 2014 | | 2014 |
Nature inspired metaheuristics for combinatorial optimization and design in VLSI LL Laudis Chennai, 0 | | |