| Interstellar: Using halide's scheduling language to analyze dnn accelerators X Yang, M Gao, Q Liu, J Setter, J Pu, A Nayak, S Bell, K Cao, H Ha, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 217 | 2020 |
| DNN dataflow choice is overrated X Yang, M Gao, J Pu, A Nayak, Q Liu, SE Bell, JO Setter, K Cao, H Ha, ... arXiv preprint arXiv:1809.04070 6, 5, 2018 | 101 | 2018 |
| Hardware trojan detection in third-party digital intellectual property cores by multilevel feature analysis X Chen, Q Liu, S Yao, J Wang, Q Xu, Y Wang, Y Liu, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 64 | 2017 |
| FASTrust: Feature analysis for third-party IP trust verification S Yao, X Chen, J Zhang, Q Liu, J Wang, Q Xu, Y Wang, H Yang 2015 IEEE International Test Conference (ITC), 1-10, 2015 | 46 | 2015 |
| Creating an agile hardware design flow R Bahr, C Barrett, N Bhagdikar, A Carsello, R Daly, C Donovick, D Durst, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 29 | 2020 |
| Aha: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers K Koul, J Melchert, K Sreedhar, L Truong, G Nyengele, K Zhang, Q Liu, ... ACM Transactions on Embedded Computing Systems 22 (2), 1-34, 2023 | 17 | 2023 |
| Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a coarse-grained reconfigurable array for flexible acceleration of dense linear algebra A Carsello, K Feng, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 15 | 2022 |
| Low-overhead implementation of logic encryption using gate replacement techniques X Chen, Q Liu, Y Wang, Q Xu, H Yang 2017 18th International Symposium on Quality Electronic Design (ISQED), 257-263, 2017 | 13 | 2017 |
| Unified buffer: Compiling image processing and machine learning applications to push-memory accelerators Q Liu, J Setter, D Huff, M Strange, K Feng, M Horowitz, P Raina, F Kjolstad ACM Transactions on Architecture and Code Optimization 20 (2), 1-26, 2023 | 8 | 2023 |
| Taeyoung Kong K Koul, J Melchert, K Sreedhar, L Truong, G Nyengele, K Zhang, Q Liu, ... Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas …, 2023 | 5 | 2023 |
| Compiling halide programs to push-memory accelerators Q Liu, D Huff, J Setter, M Strange, K Feng, K Sreedhar, Z Wang, K Zhang, ... arXiv preprint arXiv:2105.12858, 2021 | 4 | 2021 |
| Automating System Configuration. N Tsiskaridze, M Strange, M Mann, K Sreedhar, Q Liu, M Horowitz, ... FMCAD, 102-111, 2021 | 2 | 2021 |
| Cascade: An application pipelining toolkit for coarse-grained reconfigurable arrays J Melchert, Y Mei, K Koul, Q Liu, M Horowitz, P Raina IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| Amber: Coarse-grained reconfigurable array-based soc for dense linear algebra acceleration K Feng, A Carsello, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Hot Chips 34 Symposium (HCS), 1-30, 2022 | 1 | 2022 |
| COMPILING APPLICATIONS TO RECONFIGURABLE PUSH-MEMORY ACCELERATORS Q Liu STANFORD UNIVERSITY, 2023 | | 2023 |
| Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra K Feng, T Kong, K Koul, J Melchert, A Carsello, Q Liu, G Nyengele, ... IEEE Journal of Solid-State Circuits, 2023 | | 2023 |
Mark HorowitzProfessor of Electrical Engineering and Computer ScienceVerified email at ee.stanford.edu
