| Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders KV Gowreesrinivas, P Samundiswary 2016 International Conference on Control, Instrumentation, Communication and …, 2016 | 11 | 2016 |
| Comparative performance analysis of multiplexer based single precision floating point multipliers KV Gowreesrinivas, P Samundiswary 2017 International conference of Electronics, Communication and Aerospace …, 2017 | 8 | 2017 |
| FPGA implementation of single-precision floating point multiplication with Karatsuba algorithm using vedic mathematics KV Gowreesrinivas, P Samundiswary Smart Computing and Informatics: Proceedings of the First International …, 2018 | 4 | 2018 |
| Comparative analysis of single precision floating point multiplication using compressor techniques KV Gowreesrinivas, P Samundiswary 2017 International Conference on Wireless Communications, Signal Processing …, 2017 | 4 | 2017 |
| Design and analysis of turbo encoder using Xilinx ISE PP Kumar, KV Gowreesrinivas, P Samundiswary 2016 International Conference on Control, Instrumentation, Communication and …, 2016 | 4 | 2016 |
| High speed multipliers using counters based on symmetric stacking D KavyaShree, P Samundiswary, KV Gowreesrinivas 2019 International Conference on Computer Communication and Informatics …, 2019 | 3 | 2019 |
| Resource efficient single precision floating point multiplier using Karatsuba algorithm VK Gowreesrinivas, P Samundiswary Indonesian Journal of Electrical Engineering and Informatics (IJEEI) 6 (3 …, 2018 | 3 | 2018 |
| Design and analysis of single precision floating point multiplication using Karatsuba algorithm and parallel prefix adders KV Gowreesrinivas, P Samundiswary 2017 Fourth International Conference on Signal Processing, Communication and …, 2017 | 3 | 2017 |
| Improvised hierarchy of floating point multiplication using 5: 3 compressor KV Gowreesrinivas, S P International Journal of Electronics Letters 10 (1), 87-100, 2022 | 2 | 2022 |
| FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders KV Gowreesrinivas, S Srinivas, P Samundiswary Engineering, Technology & Applied Science Research 13 (3), 10698-10702, 2023 | 1 | 2023 |
| Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm KV Gowreesrinivas, P Samundiswary 2018 9th International Conference on Computing, Communication and Networking …, 2018 | 1 | 2018 |
| Design and Implementation of Hybrid Full Adder Based 16-bit Multiplication Using FPGA KV Gowreesrinivas, BU Sri, S Saideepak, G Tarun, IS Sagar 2023 IEEE Devices for Integrated Circuit (DevIC), 451-454, 2023 | | 2023 |
| FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors P Sairam, K Manikumar, YS Reddy, BU Narayana, KV Gowreesrinivas 2023 IEEE Devices for Integrated Circuit (DevIC), 404-407, 2023 | | 2023 |
| A safe and cost-effective algorithm for automation of LPG cylinder booking using ESP8266 SN Nalla, KV Gowreesrinivas Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2021 | | 2021 |
| Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm KV Gowreesrinivas, P Samundiswary Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2021 | | 2021 |
| Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba KV Gowreesrinivas, P Samundiswary Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2020 | | 2020 |
| Power analysis of single precision floating point multiplication using Vedic with proposed techniques PS K V Gowreesrinivas International Journal of Engineering & Technology 7 (3.29), 443-446, 2018 | | 2018 |
| Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques KV Gowreesrinivas, P Samundiswary Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2018 | | 2018 |
| Low Power Low Area Novel Multiplier for DSP Applications KV Gowreesrinivas, K Anusudha Programmable Device Circuits and Systems, 162-166, 2013 | | 2013 |
