| A review on power optimization of linear feedback shift register (LFSR) for low power built in self test (BIST) T Saraswathi, K Ragini, CG Reddy 2011 3rd International Conference on Electronics Computer Technology 6, 172-176, 2011 | 27 | 2011 |
| ULTRA LOW POWER DIGITAL LOGIC CIRCUITS IN SUB-THRESHOLD FOR BIOMEDICAL APPLICATIONS. K Ragini, BK Madhavi Journal of Theoretical & Applied Information Technology 5 (5), 2009 | 15 | 2009 |
| Design and Implementation of Ternary Logic Circuits for VLSI Applications G Thrishala, K Ragini International Journal of Innovative Technology and Exploring Engineering …, 2020 | 10 | 2020 |
| Variable threshold MOSFET approach (through dynamic threshold MOSFET) for universal logic gates K Ragini, M Satyam, BC Jinaga arXiv preprint arXiv:1003.6030, 2010 | 8 | 2010 |
| Design of a novel high-speed-and energy-efficient 32-bit carry-skip adder B Sanjana, K Ragini Innovations in Electronics and Communication Engineering: Proceedings of the …, 2019 | 7 | 2019 |
| Low power and high speed full adder using new XOR and XNOR Gates P Juveria, K Ragini International Journal of Innovative Technology and Exploring Engineering …, 2019 | 6 | 2019 |
| Comparative Analysis of 32 bit carry lookahead adder using high speed constant delay logic VR Rao, K Ragini International Journal of Science, Engineering and Technology Research …, 2014 | 5 | 2014 |
| Emerging NanoFETs and Electrostatics Influencing Nanoscale Transistors: A Review D Amuru, K Ragini, PCS Reddy International Journal of Engineering and Applied Sciences 3 (2), 257721, 2016 | 3 | 2016 |
| VTMOS Circuits Realization through DTMOS Circuits K Ragini, M Satyam, BC Jinaga International Journal of Engineering Research & Technology (IJERT) 2 (9 …, 2013 | 3 | 2013 |
| Design and Implementation of RNB multiplier Using NP Domino logic B Majji, K Ragini 2022 International Conference on Recent Trends in Microelectronics …, 2022 | 1 | 2022 |
| Design of a low power and high speed 512-bit shift register using static differential sense amplifier shared pulsed latch circuit B Keerthi, K Ragini IOSR J VLSI Signal Process (IOSR-JVSP) 8 (2), 38-43, 2018 | 1 | 2018 |
| Analysis of MIMO-OFDM under Rayleigh Fading in 4G Cellular Systems DMS Babu, K Ragini 21st International Conference on Electrical Electronics Communication …, 2016 | 1 | 2016 |
| Comparative analysis of low-power cmos&dtmos full adder circuits at 180nm and 45nm technologies M Mounika, K Ragini International Journal of Engineering Research and General Science 3, 465-476, 2016 | 1 | 2016 |
| Security and performance analysis of identity based schemes in sensor networks K Ragini, S Sivasankar 2015 International Conference on Innovations in Information, Embedded and …, 2015 | 1 | 2015 |
| Variable Threshold MOS Circuits K Ragini, M Satyam, BC Jinaga International Journal of Modern Engineering Research (IJMER) Vol 3, 0 | 1 | |
| Physical layer security based on full duplex and half-duplex multi relay assisted OFDM system K Ragini, K Gunaseelan, R Dhanusuya Automatika 64 (4), 1158-1170, 2023 | | 2023 |
| Implementation of Unbiased Rounding for 64-Bit Floating Point Adder V Dasu, K Ragini 2022 International Conference on Recent Trends in Microelectronics …, 2022 | | 2022 |
| Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder V Dasu, K Ragini International Conference on Intelligent Computing and Communication, 461-468, 2022 | | 2022 |
| Analysis of Serial-In Parallel-Out Finite Field Multiplier Using Various Domino Logic Styles B Majji, K Ragini International Conference on Intelligent Computing and Communication, 241-249, 2022 | | 2022 |
| Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm V Durgam, K Ragini ECS Transactions 107 (1), 16251, 2022 | | 2022 |
