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Igor Aleksejev
Igor Aleksejev
Researcher of Computer Science, Tallinn University of Technology
Verified email at ttu.ee - Homepage
Title
Cited by
Cited by
Year
Fast extended test access via JTAG and FPGAs
S Devadze, A Jutman, I Aleksejev, R Ubar
2009 International Test Conference, 1-7, 2009
262009
FPGA-based synthetic instrumentation for board test
I Aleksejev, A Jutman, S Devadze, S Odintsov, T Wenzel
2012 IEEE International Test Conference, 1-10, 2012
222012
System and method for optimized board test and configuration
S Devadze, A Jutman, I Aleksejev, K Shibin, T Wenzel
US Patent 9,164,858, 2015
142015
Virtual reconfigurable scan-chains on FPGAs for optimized board test
I Aleksejev, S Devadze, A Jutman, K Shibin
2015 16th Latin-American Test Symposium (LATS), 1-6, 2015
62015
Turning JTAG inside out for fast extended test access
S Devadze, A Jutman, I Aleksejev, R Ubar
2009 10th Latin American Test Workshop, 1-6, 2009
62009
Embedded synthetic instruments for Board-Level testing
A Jutman, S Devadze, I Aleksejev, T Wenzel
2012 17th IEEE European Test Symposium (ETS), 1-1, 2012
52012
Optimization of the store-and-generate based built-in self-test
R Ubar, G Jervan, H Kruus, E Orasson, I Aleksejev
2006 International Biennial Baltic Electronics Conference, 1-4, 2006
52006
Reseeding using compaction of pre-generated LFSR sub-sequences
A Jutman, I Aleksejev, J Raik, R Ubar
2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008
42008
Teaching digital test with BIST analyzer
A Jutman, A Tsertov, A Tsepurov, I Aleksejev, R Ubar, HD Wuttke
2008 19th EAEEIE Annual Conference, 123-128, 2008
42008
BIST analyzer: A training platform for SoC testing
A Jutman, A Tsertov, A Tsepurov, I Aleksejev, R Ubar, HD Wuttke
2007 37th Annual Frontiers In Education Conference-Global Engineering …, 2007
42007
Embedded instrumentation toolbox for screening marginal defects and outliers for production
S Odintsov, A Jutman, S Devadze, I Aleksejev
2017 IEEE AUTOTESTCON, 1-9, 2017
32017
On coverage of timing related faults at board level
A Jutman, I Aleksejev, S Devadze
2016 21th IEEE European Test Symposium (ETS), 1-2, 2016
32016
FPGA-based Embedded Virtual Instrumentation
I Aleksejev
Tut Press, 2013
32013
Application of Sequential Test Set Compaction to LFSR Reseeding
I Aleksejev, A Jutman, J Raik, R Ubar
2008 NORCHIP, 102-107, 2008
32008
Run-time reconfigurable instruments for advanced board-level testing
I Aleksejev, A Jutman, S Devadze
IEEE Instrumentation & Measurement Magazine 20 (4), 23-30, 2017
22017
Sequential Test Set Compaction in LFSR Reseeding
A Jutman, I Aleksejev, J Raik
Design and Test Technology for Dependable Systems-on-Chip, 476-493, 2011
22011
E-Learning Environment for WEB-Based Study of Testing
R Ubar, A Jutman, J Raik, S Devadze, M Jenihhin, I Aleksejev, ...
Proc. of the 8th European Workshop on Microelectronics Education-EWME 2010 …, 2010
22010
Ways for board and system test to benefit from FPGA embedded instrumentation
H Ehrenberg, S Odintsov, S Devadze, A Jutman, I Aleksejev, T Wenzel
2019 IEEE AUTOTESTCON, 1-10, 2019
12019
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures
I Aleksejev, S Devadze, A Jutman, K Shibin
Journal of Electronic Testing 32, 245-255, 2016
12016
Complex delay fault reasoning with sequential 7-valued algebra
J Kousaar, R Ubar, I Aleksejev
2015 16th Latin-American Test Symposium (LATS), 1-6, 2015
2015
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Articles 1–20