| A 22.5-to-32-Gb/s 3.2-pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28-nm CMOS W Rahman, D Yoo, J Liang, A Sheikholeslami, H Tamura, T Shibasaki, ... IEEE Journal of Solid-State Circuits 52 (12), 3517-3531, 2017 | 76 | 2017 |
| Ising-model optimizer with parallel-trial bit-sieve engine S Matsubara, H Tamura, M Takatsu, D Yoo, B Vatankhahghadim, ... Complex, Intelligent, and Software Intensive Systems: Proceedings of the …, 2018 | 69 | 2018 |
| A 36-Gb/s adaptive baud-rate CDR with CTLE and 1-tap DFE in 28-nm CMOS D Yoo, M Bagherbeik, W Rahman, A Sheikholeslami, H Tamura, ... IEEE Solid-State Circuits Letters 2 (11), 252-255, 2019 | 47 | 2019 |
| A 30Gb/s 2x half-baud-rate CDR D Yoo, M Bagherbeik, W Rahman, A Sheikholeslami, H Tamura, ... 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 10 | 2019 |
| Complex, Intelligent, and Software Intensive Systems S Matsubara, H Tamura, M Takatsu, D Yoo, B Vatankhahghadim, ... Springer, 2018 | 7 | 2018 |
| High-Speed Baud-Rate Clock and Data Recovery D Yoo University of Toronto (Canada), 2018 | | 2018 |
| ISSCC 2019/SESSION 6/ULTRA-HIGH-SPEED WIRELINE/6.8 D Yoo, M Bagherbeik, W Rahman, A Sheikholeslami, H Tamura, ... | | |
| ISSCC 2017/SESSION 6/ULTRA-HIGH-SPEED WIRELINE/6.6 W Rahman, D Yoo, J Liang, A Sheikholeslami, H Tamura, T Shibasaki, ... | | |
