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Chirag Garg
Chirag Garg
EECS, University of California Berkeley ||Micron Technology || IIT Roorkee
Verified email at berkeley.edu
Title
Cited by
Cited by
Year
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET
C Garg, N Chauhan, S Deng, AI Khan, S Dasgupta, A Bulusu, K Ni
IEEE Electron Device Letters 42 (8), 1160-1163, 2021
322021
BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective
N Chauhan, N Bagga, S Banchhor, C Garg, A Sharma, A Datta, ...
Nanotechnology 33 (8), 085203, 2021
142021
Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET
C Garg, N Chauhan, A Sharma, S Banchhor, A Doneria, S Dasgupta, ...
IEEE Transactions on Electron Devices, 1 - 7, 2021
122021
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI
N Chauhan, C Garg, K Ni, AK Behera, S Yadav, S Banchhor, N Bagga, ...
2022 IEEE International Reliability Physics Symposium (IRPS), P23-1-P23-6, 2022
62022
How to Achieve Moving Current Filament in High Voltage LDMOS Devices: Physical Insights & Design Guidelines for Self-Protected Concepts
NK Kranthi, C Garg, BS Kumar, A Salman, G Boselli, M Shrivastava
2020 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2020
52020
Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack
LC Wang, W Li, N Shanker, SS Cheema, SL Hsu, S Volkman, U Sikder, ...
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023
22023
Boost in Carrier Velocity due to Electrostatic Effects of Negative Capacitance Gate Stack
C Garg, S Cheema, N Shanker, W Li, C Hu, S Salahuddin
IEEE Electron Device Letters, 1 - 1, 2024
2024
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