| Design obfuscation through selective post-fabrication transistor-level programming MM Shihab, J Tian, GR Reddy, B Hu, W Swartz, BC Schaefer, C Sechen, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 528-533, 2019 | 33 | 2019 |
| Functional obfuscation of hardware accelerators through selective partial design extraction onto an embedded fpga B Hu, J Tian, M Shihab, GR Reddy, W Swartz, Y Makris, BC Schaefer, ... Proceedings of the 2019 on Great Lakes Symposium on VLSI, 171-176, 2019 | 32 | 2019 |
| An efficient MILP-based aging-aware floorplanner for multi-context coarse-grained runtime reconfigurable FPGAs B Hu, M Shihab, Y Makris, BC Schaefer, C Sechen 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 5 | 2020 |
| Toward Accurate Timing Analysis for Transistor-Level Programmable Fabrics Q Huang, J Tian, T Broadfoot, X Xu, B Hu, M Shihab, A Jane, V Salimath, ... 2022 IEEE 15th Dallas Circuit And System Conference (DCAS), 1-6, 2022 | 1 | 2022 |
| Thermal-aware Placement and High Level Synthesis for Hardware Security B Hu | | 2021 |
| Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage B Hu, M Shihab, Y Makris, BC Schaefer, C Sechen 2019 International Conference on Field-Programmable Technology (ICFPT), 291-294, 2019 | | 2019 |
