| BLADE: An in-cache computing architecture for edge devices WA Simon, YM Qureshi, M Rios, A Levisse, M Zapater, D Atienza IEEE Transactions on Computers 69 (9), 1349-1363, 2020 | 66 | 2020 |
| Gem5-x: A gem5-based system level simulation framework to optimize many-core platforms YM Qureshi, WA Simon, M Zapater, D Atienza, K Olcoz 2019 Spring Simulation Conference (SpringSim), 1-12, 2019 | 39 | 2019 |
| A fast, reliable and wide-voltage-range in-memory computing architecture W Simon, J Galicia, A Levisse, M Zapater, D Atienza Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 37 | 2019 |
| BLADE: A bitline accelerator for devices on the edge WA Simon, YM Qureshi, A Levisse, M Zapater, D Atienza Proceedings of the 2019 on Great Lakes Symposium on VLSI, 207-212, 2019 | 28 | 2019 |
| Gem5-x: A many-core heterogeneous simulation platform for architectural exploration and optimization YM Qureshi, WA Simon, M Zapater, K Olcoz, D Atienza ACM Transactions on Architecture and Code Optimization (TACO) 18 (4), 1-27, 2021 | 20 | 2021 |
| Thermal characterization of next-generation workloads on heterogeneous MPSoCs A Iranfar, F Terraneo, WA Simon, L Dragić, I Piljić, M Zapater, ... 2017 International Conference on Embedded Computer Systems: Architectures …, 2017 | 14 | 2017 |
| An associativity-agnostic in-cache computing architecture optimized for multiplication M Rios, W Simon, A Levisse, M Zapater, D Atienza 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 13 | 2019 |
| 1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA F Angiolini, A Ibrahim, W Simon, AC Yüzügüler, M Arditi, JP Thiran, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 12 | 2017 |
| Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer W Simon, AC Yüzügüler, A Ibrahim, F Angiolini, M Arditi, JP Thiran, ... 2016 26th International Conference on Field Programmable Logic and …, 2016 | 10 | 2016 |
| Functionality enhanced memories for edge-AI embedded systems A Levisse, M Rios, WA Simon, PE Gaillardon, D Atienza 2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2019 | 9 | 2019 |
| Hdtorch: Accelerating hyperdimensional computing with gp-gpus for design space exploration WA Simon, U Pale, T Teijeiro, D Atienza Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 6 | 2022 |
| Single-FPGA complete 3D and 2D medical ultrasound imager A Ibrahim, W Simon, D Doy, E Pignat, F Angiolini, M Arditi, JP Thiran, ... 2017 Conference on Design and Architectures for Signal and Image Processing …, 2017 | 6 | 2017 |
| Exact neural networks from inexact multipliers via fibonacci weight encoding WA Simon, V Ray, A Levisse, G Ansaloni, M Zapater, D Atienza 2021 58th ACM/IEEE Design Automation Conference (DAC), 805-810, 2021 | 5 | 2021 |
| A machine learning-based strategy for efficient resource management of video encoding on heterogeneous MPSoCs A Iranfar, WA Simon, M Zapater, D Atienza 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 4 | 2018 |
| Single-FPGA 3D ultrasound beamformer AC Yüzügüler, W Simon, A Ibrahim, F Angiolini, M Arditi, JP Thiran, ... 2016 26th International Conference on Field Programmable Logic and …, 2016 | 2 | 2016 |
| Associativity-agnostic in-cache computing memory architecture optimized for multiplication MA Rios, WA Simon, AS Levisse, M Zapater, DA Alonso US Patent 11,211,115, 2021 | 1 | 2021 |
| Memory chip or memory array for wide-voltage range in-memory computing using bitline technology WA Simon, MA Rios, AS Levisse, M Zapater, D Atienza Alonso | 1 | 2021 |
| 1024-channel single 5W FPGA towards high-quality portable 3D ultrasound platform A Ibrahim, W Simon, AC Yüzügüler, M Arditi, JP Thiran, G De Micheli 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 | 1 | 2017 |
| In-Memory Hardware and Architectural Extensions for Workloads Acceleration WA Simon EPFL, 2022 | | 2022 |
| Memory chip or memory array for wide-voltage range in-memory computing using bitline technology WA Simon, MA Rios, AS Levisse, M Zapater, DA Alonso US Patent 11,094,355, 2021 | | 2021 |
David AtienzaProfessor of Electrical and Computer Engineering, EPFLVerified email at epfl.ch
