| Low power floating point computation sharing multiplier for signal processing applications S Sivanantham, KJ Naidu, S Balamurugan, DB Phaneendra International Journal of Engineering and Technology 5 (2), 979-985, 2013 | 20 | 2013 |
| Partial reconfigurable implementation of IEEE802. 11g OFDM S Sivanantham, R Adarsh, S Bhargav, KJ Naidu Indian J. Sci. Technol 7 (4), 63-70, 2014 | 11 | 2014 |
| On Chip DC-DC Converter with High Switching Frequency and Low Ripple Voltage KJ Naidu, HM Kittur Indian Journal of Science and Technology 9, 5, 2016 | 4 | 2016 |
| A 90% efficiency, 250 MHz on-chip adaptive switched capacitor based DC–DC converter KJ Naidu, HM Kittur Analog Integrated Circuits and Signal Processing 89 (2), 451-460, 2016 | 3 | 2016 |
| Power reduction using DVFS with a producer-consumer FIFO P Pillamari, KJ Naidu, HM Kittur 2011 International Conference on Signal Processing, Communication, Computing …, 2011 | 3 | 2011 |
| Design of Low Drop-Out voltage regulator KJ Naidu, HM Kittur, P Avinash NISCAIR-CSIR, India, 2015 | 1 | 2015 |
| Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS KJ Naidu, HM Kittur Analog Integrated Circuits and Signal Processing 90 (3), 639-644, 2017 | | 2017 |
| DESIGN AND VERIFICATION OF MASTER BLOCK IN ETHERNET MANAGEMENT INTERFACE USING UVM IS Ramaswamy, KJ Naidu Far East Journal of Electronics and Communications 16 (1), 37, 2016 | | 2016 |
| Low power floating point computation sharing multiplier for signal processing applications. S Sathasivam, SJ Dilipbhai, BA Jitendrabha, S Sinha, A Gougam, ... Asian Journal of Scientific Research 9 (1), 40-42, 2010 | | 2010 |
