| Embedded deterministic test J Rajski, J Tyszer, M Kassab, N Mukherjee IEEE transactions on computer-aided design of integrated circuits and …, 2004 | 653 | 2004 |
| Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers S Hellebrand, J Rajski, S Tarnick, S Venkataraman, B Courtois IEEE Transactions on Computers 44 (2), 223-233, 1995 | 584 | 1995 |
| Embedded deterministic test for low cost manufacturing test J Rajski, J Tyszer, M Kassab, N Mukherjee, R Thompson, KH Tsai, ... Proceedings. International Test Conference, 301-310, 2002 | 486 | 2002 |
| Logic BIST for large industrial designs: Real issues and case studies G Hetherington, T Fryars, N Tamarapalli, M Kassab, A Hassan, J Rajski International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999 | 414 | 1999 |
| Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers S Hellebrand, S Tarnick, J Rajski, B Courtois Proceedings-International-Test-Conference-1992-, 120-9, 1992 | 347 | 1992 |
| Preferred fill: A scalable method to reduce capture power for scan based designs S Remersaro, X Lin, Z Zhang, SM Reddy, I Pomeranz, J Rajski 2006 IEEE International Test Conference, 1-10, 2006 | 300 | 2006 |
| Arithmetic built-in self-test for embedded systems J Rajski, J Tyszer Prentice-Hall, Inc., 1998 | 232 | 1998 |
| Testing and diagnosis of interconnects using boundary scan architecture A Hassan, J Rajski, VK Agarwal International Test Conference 1988 Proceeding@ m_New Frontiers in Testing …, 1988 | 222 | 1988 |
| High-frequency, at-speed scan testing X Lin, R Press, J Rajski, P Reuter, T Rinderknecht, B Swanson, ... IEEE Design & Test of Computers 20 (5), 17-25, 2003 | 215 | 2003 |
| Timing-aware ATPG for high quality at-speed testing of small delay defects X Lin, KH Tsai, C Wang, M Kassab, J Rajski, T Kobayashi, R Klingenberg, ... 2006 15th Asian Test Symposium, 139-146, 2006 | 210 | 2006 |
| Impact of multiple-detect test patterns on product quality B Benware, C Schuermyer, S Ranganathan, R Madge, P Krishnamurthy, ... International Test Conference, 2003. Proceedings. ITC 2003., 1031-1031, 2003 | 210 | 2003 |
| Test pattern compression for an integrated circuit test environment J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,327,687, 2001 | 206* | 2001 |
| Arithmetic built-in self test of multiple scan-based integrated circuits J Rajski, J Tyszer US Patent 5,991,898, 1999 | 203* | 1999 |
| A method of fault analysis for test generation and fault diagnosis H Cox, J Rajski IEEE transactions on computer-aided design of integrated circuits and …, 1988 | 198 | 1988 |
| Method and apparatus for selectively compacting test responses J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,557,129, 2003 | 190* | 2003 |
| Constructive multi-phase test point insertion for scan-based BIST N Tamarapalli, J Rajski Proceedings International Test Conference 1996. Test and Design Validity …, 1996 | 184 | 1996 |
| Cell-aware test F Hapke, W Redemund, A Glowatz, J Rajski, M Reese, M Hustava, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 182 | 2014 |
| Decompressor/PRPG for applying pseudo-random and deterministic test patterns J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,684,358, 2004 | 182* | 2004 |
| Convolutional compaction of test responses J Rajski, J Tyszer, C Wang, SM Reddy International Test Conference, 745-754, 2003 | 158 | 2003 |
| Parallel decompressor and related methods and apparatuses J Rajski, J Tyszer US Patent 5,991,909, 1999 | 155 | 1999 |
Nilanjan MukherjeeSenior Engineering Director, Siemens Digital Industries SoftwareVerified email at mentor.com
