| Machine-learning-based hotspot detection using topological classification and critical feature extraction YT Yu, GH Lin, IHR Jiang, C Chiang Proceedings of the 50th annual design automation conference, 1-6, 2013 | 143 | 2013 |
| Accurate process-hotspot detection using critical design rule extraction YT Yu, YC Chan, S Sinha, IHR Jiang, C Chiang Proceedings of the 49th Annual Design Automation Conference, 1167-1172, 2012 | 89 | 2012 |
| INTEGRA: Fast multibit flip-flop clustering for clock power saving IHR Jiang, CL Chang, YM Yang IEEE Transactions on computer-aided design of integrated circuits and …, 2012 | 61 | 2012 |
| Generic integer linear programming formulation for 3D IC partitioning IHR Jiang 2009 IEEE International SOC Conference (SOCC), 321-324, 2009 | 45 | 2009 |
| INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs IHR Jiang, CL Chang, YM Yang, EYW Tsai, LSF Chen Proceedings of the 2011 international symposium on Physical design, 115-122, 2011 | 33 | 2011 |
| Graph-based modeling, scheduling, and verification for intersection management of intelligent vehicles YT Lin, H Hsu, SC Lin, CW Lin, IHR Jiang, C Liu ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-21, 2019 | 29 | 2019 |
| WiT: optimal wiring topology for electromigration avoidance IHR Jiang, HY Chang, CL Chang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (4), 581-592, 2011 | 29 | 2011 |
| FF-bond: Multi-bit flip-flop bonding at placement CC Tsai, Y Shi, G Luo, IHR Jiang Proceedings of the 2013 ACM International symposium on Physical Design, 147-153, 2013 | 27 | 2013 |
| iClaire: A fast and general layout pattern classification algorithm WC Chang, IHR Jiang, YT Yu, WF Liu Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 26 | 2017 |
| iTimerC: Common path pessimism removal using effective reduction methods YM Yang, YW Chang, IHR Jiang 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 600-605, 2014 | 25 | 2014 |
| iTimerC 2.0: Fast incremental timing and CPPR analysis PY Lee, IHR Jiang, CR Li, WL Chiu, YM Yang 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 890-894, 2015 | 23 | 2015 |
| A clustering-and probability-based approach for time-multiplexed FPGA partitioning MCT Chao, GM Wu, IHR Jiang, YW Chang 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 23 | 1999 |
| Matching-based minimum-cost spare cell selection for design changes IHR Jiang, HY Chang, LG Chang, HB Hung Proceedings of the 46th Annual Design Automation Conference, 408-411, 2009 | 22 | 2009 |
| Fast and accurate wire timing estimation on tree and non-tree net structures HH Cheng, IHR Jiang, O Ou 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 20 | 2020 |
| Resource-aware functional ECO patch generation AC Cheng, IHR Jiang, JY Jou 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 18 | 2016 |
| PushPull: Short path padding for timing error resilient circuits YM Yang, IHR Jiang, ST Ho Proceedings of the 2013 ACM International symposium on Physical Design, 50-57, 2013 | 18 | 2013 |
| Analog placement and global routing considering wiring symmetry YM Yang, IHR Jiang 2010 11th International Symposium on Quality Electronic Design (ISQED), 618-623, 2010 | 18 | 2010 |
| Multiple patterning layout decomposition considering complex coloring rules and density balancing IHR Jiang, HY Chang IEEE transactions on computer-aided design of integrated circuits and …, 2017 | 17 | 2017 |
| OpenDesign Flow Database: The infrastructure for VLSI design and design automation research J Jung, IHR Jiang, GJ Nam, VN Kravets, L Behjat, YL Li 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016 | 17 | 2016 |
| Multiple patterning layout decomposition considering complex coloring rules HY Chang, IHR Jiang Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 17 | 2016 |
