| An energy efficient ECG signal processor detecting cardiovascular diseases on smartphone SK Jain, B Bhaumik IEEE transactions on biomedical circuits and systems 11 (2), 314-323, 2016 | 69 | 2016 |
| A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology SK Jain, P Agarwal 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 64 | 2006 |
| Efficient word lines, bit line and precharge tracking in self-timed memory device SK Jain, D Dwivedi US Patent 8,040,746, 2011 | 30 | 2011 |
| Input trigger independent low leakage memory circuit SK Jain, G Vikas, A Khanuja US Patent 9,001,569, 2015 | 17 | 2015 |
| QRS complex identification in electrocardiogram signals B Bhaumik, SK Jain US Patent 9,414,761, 2016 | 15 | 2016 |
| An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection SK Jain, B Bhaumik Healthcare Technology Letters 3 (1), 77-84, 2016 | 14 | 2016 |
| An ultra low power ECG signal processor design for cardiovascular disease detection SK Jain, B Bhaumik 2015 37th Annual International Conference of the IEEE Engineering in …, 2015 | 13 | 2015 |
| Aggressor aware repeater circuits for improving on-chip bus performance and robustness A Katoch, SK Jain, M Meijer ESSCIRC 2004-29th European Solid-State Circuits Conference (IEEE Cat. No …, 2003 | 8 | 2003 |
| Memory device and compensation method therein SK Jain, A Katoch US Patent 10,522,202, 2019 | 7 | 2019 |
| Low power read scheme for read only memory (ROM) A Sharma, SK Jain, M Rana US Patent 7,940,545, 2011 | 7 | 2011 |
| A novel circuit to optimize access time and decoding schemes in memories SK Jain, K Srivastva, S Kainth 2010 23rd International Conference on VLSI Design, 117-121, 2010 | 6 | 2010 |
| Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication A Katoch, M Meijer, SK Jain 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 5 | 2005 |
| Clamping circuit to counter parasitic coupling A Katoch, RIMP Meijer, SK Jain US Patent 7,429,885, 2008 | 4 | 2008 |
| Systems and methods for controlling power management operations in a memory device SK Jain, SP Singh, A Katoch US Patent 11,309,000, 2022 | 2 | 2022 |
| Memory architecture SK Jain US Patent 11,164,614, 2021 | 2 | 2021 |
| Sensing circuit for semiconductor memory AK Gupta, D Dwivedi, SK Jain, Y Mishra US Patent App. 12/620,539, 2010 | 2 | 2010 |
| Low power scheme for power down in integrated dual rail SRAMs SK Jain US Patent 11,682,434, 2023 | 1 | 2023 |
| Bit line pre-charge circuit for power management modes in multi bank SRAM SK Jain, R Jain, A Achyuthan, A Katoch US Patent 11,626,158, 2023 | 1 | 2023 |
| Memory device and power management method using the same SK Jain US Patent 11,532,335, 2022 | 1 | 2022 |
| Memory circuit including an array control inhibitor SK Jain, CM O'connell US Patent 11,403,033, 2022 | 1 | 2022 |
