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Tianyu Jia
Tianyu Jia
Assistant Professor of School of Integrated Circuits, Peking University
Verified email at pku.edu.cn - Homepage
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Cited by
Year
Edgebert: Sentence-level energy optimizations for latency-aware multi-task nlp inference
T Tambe, C Hooper, L Pentecost, T Jia, EY Yang, M Donato, V Sanh, ...
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021
792021
Analyzing and improving fault tolerance of learning-based navigation systems
Z Wan, A Anwar, YS Hsiao, T Jia, VJ Reddi, A Raychowdhury
2021 58th ACM/IEEE Design Automation Conference (DAC), 841-846, 2021
172021
A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC
T Jia, P Mantovani, MC Dos Santos, D Giri, J Zuckerman, EJ Loscalzo, ...
ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022
162022
An instruction-driven adaptive clock management through dynamic phase scaling and compiler assistance for a low power microprocessor
T Jia, R Joseph, J Gu
IEEE Journal of Solid-State Circuits 54 (8), 2327-2338, 2019
162019
A fully integrated buck regulator with 2-GHz resonant switching for low-power applications
T Jia, J Gu
IEEE Journal of Solid-State Circuits 53 (9), 2663-2674, 2018
162018
Mavfi: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles
YS Hsiao, Z Wan, T Jia, R Ghosal, A Mahmoud, A Raychowdhury, ...
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
152023
7.8 A 22nm delta-sigma computing-in-memory (Δ∑ CIM) SRAM macro with near-zero-mean outputs and LSB-first ADCs achieving 21.38 TOPS/W for 8b-MAC edge AI processing
P Chen, M Wu, W Zhao, J Cui, Z Wang, Y Zhang, Q Wang, J Ru, L Shen, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 140-142, 2023
152023
A compact stacked bidirectional antenna for dual-polarized WLAN applications
T Jia, X Li
Progress In Electromagnetics Research C 44, 95-108, 2013
152013
Ncpu: An embedded neural cpu architecture on resource-constrained low power devices for real-time end-to-end performance
T Jia, Y Ju, R Joseph, J Gu
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020
142020
31.3 A compute-adaptive elastic clock-chain technique with dynamic timing enhancement for 2D PE-array-based accelerators
T Jia, Y Ju, J Gu
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 482-484, 2020
112020
Compiler-guided instruction-level clock scheduling for timing speculative processors
Y Fan, T Jia, J Gu, S Campanoni, R Joseph
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
112018
A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique
T Jia, Y Ju, J Gu
IEEE Journal of Solid-State Circuits 56 (1), 55-65, 2020
102020
A RF-MEMS based dual-band tunable filter with independently controllable passbands
T Jia, J Ye, Z Liu
2014 12th IEEE International Conference on Solid-State and Integrated …, 2014
102014
An adaptive clock management scheme exploiting instruction-based dynamic timing slack for a general-purpose graphics processor unit with deep pipeline and out-of-order execution
T Jia, R Joseph, J Gu
International Solid-State Circuit Conference, 2019
92019
An instruction driven adaptive clock phase scaling with timing encoding and online instruction calibration for a low power microprocessor
T Jia, R Joseph, J Gu
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC), 94-97, 2018
92018
Omu: A probabilistic 3d occupancy mapping accelerator for real-time octomap at the edge
T Jia, EY Yang, YS Hsiao, J Cruz, D Brooks, GY Wei, VJ Reddi
arXiv preprint arXiv:2205.03325, 2022
82022
19.4 an adaptive clock management scheme exploiting instruction-based dynamic timing slack for a general-purpose graphics processor unit with deep pipeline and out-of-order …
T Jia, R Joseph, J Gu
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 318-320, 2019
82019
Greybox design methodology: A program driven hardware co-optimization with ultra-dynamic clock management
T Jia, R Joseph, J Gu
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
82017
Supply voltage decoupling circuits for voltage droop mitigation
X Zhang, T Takken, T Jia
US Patent 10,972,083, 2021
72021
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion
K Otseidu, T Jia, J Bryne, L Hargrove, J Gu
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
72018
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