| Resonant-clock latch-based design VS Sathe, JC Kao, MC Papaefthymiou IEEE Journal of Solid-State Circuits 43 (4), 864-873, 2008 | 70 | 2008 |
| 187 MHz subthreshold-supply charge-recovery FIR WH Ma, JC Kao, VS Sathe, MC Papaefthymiou IEEE Journal of Solid-State Circuits 45 (4), 793-803, 2010 | 45 | 2010 |
| Clock distribution network architecture with clock skew management JY Chueh, J Kao, V Sathe, MC Papaefthymiou, C Ziesler US Patent 7,956,664, 2011 | 39 | 2011 |
| Clock distribution network architecture with resonant clock gating JY Chueh, J Kao, V Sathe, MC Papaefthymiou US Patent 7,719,317, 2010 | 34 | 2010 |
| Clock distribution network architecture for resonant-clocked systems JY Chueh, J Kao, V Sathe, MC Papaefthymiou US Patent 7,719,316, 2010 | 32 | 2010 |
| Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic JC Kao, WH Ma, VS Sathe, M Papaefthymiou IEEE transactions on very large scale integration (VLSI) systems 20 (6), 977-988, 2011 | 23 | 2011 |
| A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic WH Ma, JC Kao, VS Sathe, M Papaefthymiou 2009 Symposium on VLSI Circuits, 202-203, 2009 | 23 | 2009 |
| Storage array including a local clock buffer with programmable timing GD Carpenter, FH Gebara, JC Kao, JB Kuang, KJ Nowka, LT Pang US Patent 7,668,037, 2010 | 22 | 2010 |
| Clock distribution network architecture with clock skew management JY Chueh, J Kao, V Sathe, MC Papaefthymiou, C Ziesler US Patent 8,289,063, 2012 | 21 | 2012 |
| Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance JB Kuang, JC Kao, HC Ngo, KJ Nowka US Patent 7,349,271, 2008 | 20 | 2008 |
| Cell and macro placement on fin grid KN Yang, LIN Chou-Kun, JCJ Kao, YC Tsai, CJ Chao, CH Wang US Patent 9,047,433, 2015 | 18 | 2015 |
| RF2: A 1GHz FIR filter with distributed resonant clock generator VS Sathe, JC Kao, MC Papaefthymiou 2007 IEEE Symposium on VLSI Circuits, 44-45, 2007 | 17 | 2007 |
| A resonant-clock 200MHz ARM926EJ-STM microcontroller AT Ishii, JC Kao, VS Sathe, MC Papaefthymiou 2009 Proceedings of ESSCIRC, 356-359, 2009 | 16 | 2009 |
| Channel doping extension beyond cell boundaries KN Yang, LIN Chou-Kun, JCJ Kao, YC Tsai, CJ Chao, CH Wang US Patent 8,937,358, 2015 | 15 | 2015 |
| Flip-flop with delineated layout for reduced footprint CL Liu, TW Chiang, JCJ Kao, H Zhuang, LC Lu, SC Hsieh, CM Huang US Patent 9,641,161, 2017 | 14 | 2017 |
| Integrated circuit with standard cells KN Yang, LIN Chou-Kun, JCJ Kao, YC Tsai, CJ Chao, CH Wang US Patent 8,847,284, 2014 | 14 | 2014 |
| 2.07 GHz floating-point unit with resonant-clock precharge logic CK Jerry, WH Ma, S Kim, M Papaefthymiou 2010 IEEE Asian Solid-State Circuits Conference, 1-4, 2010 | 13 | 2010 |
| Integrated circuit, system for and method of forming an integrated circuit Y Jung-Chan, TW Chiang, JCJ Kao, H Zhuang, LC Lu, LC Tien, MH Shen, ... US Patent 10,740,531, 2020 | 12 | 2020 |
| A 5.5 GS/s 28mW 5-bit flash ADC with resonant clock distribution WH Ma, JC Kao, M Papaefthymiou 2011 Proceedings of the ESSCIRC (ESSCIRC), 155-158, 2011 | 12 | 2011 |
| Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance JB Kuang, JC Kao, HC Ngo, KJ Nowka, LT Pang, J Sivagnaname US Patent 7,760,565, 2010 | 11 | 2010 |
Visvesh SatheAssociate Professor, Georgia Institute of TechnologyVerified email at gatech.edu
