| Path-balanced logic design to realize block ciphers resistant to power and timing attacks P De, C Mandal, U Prampalli IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5 …, 2019 | 11 | 2019 |
| Designing DPA resistant circuits using BDD architecture and bottom pre-charge logic P De, K Banerjee, C Mandal, D Mukhopadhyay 2013 Euromicro Conference on Digital System Design, 641-644, 2013 | 8 | 2013 |
| Secure Path Balanced BDD-Based Pre-Charge Logic for Masking P De, U Parampalli, C Mandal IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4747 - 4760, 2020 | 5 | 2020 |
| Circuits and synthesis mechanism for hardware design to counter power analysis attacks P De, K Banerjee, C Mandal, D Mukhopadhyay 2014 17th Euromicro Conference on Digital System Design, 520-527, 2014 | 2 | 2014 |
| A BDD based secure hardware design method to guard against power analysis attacks P De, K Banerjee, C Mandal 18th International Symposium on VLSI Design and Test, 1-2, 2014 | 1 | 2014 |
| Combining BDD based Circuit Synthesis Technique with Masked Dual-Rail Pre-charge Logic to Eliminate Glitches in Circuits P De, U Parampalli, C Mandal 4TH ANNUAL DOCTORAL COLLOQUIUM, 42, 2016 | | 2016 |
| Test plan for secure asynchronous adder and area-power efficient asynchronous adder P De Indian Institute of Technology, Kharagpur, 2011 | | 2011 |
Chittaranjan MandalDept of Computer Sc & Engg, IIT KharagpurVerified email at iitkgp.ac.in
