| A model for transient fault propagation in combinatorial logic M Omana, G Papasso, D Rossi, C Metra 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 111-115, 2003 | 182 | 2003 |
| Latch susceptibility to transient faults and new hardening approach M Omana, D Rossi, C Metra IEEE Transactions on Computers 56 (9), 1255-1268, 2007 | 170 | 2007 |
| High-performance robust latches M Omaña, D Rossi, C Metra IEEE Transactions on Computers 59 (11), 1455-1465, 2010 | 117 | 2010 |
| Multiple transient faults in logic: An issue for next generation ICs? D Rossi, M Omana, F Toma, C Metra 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 112 | 2005 |
| Novel Transient Fault Hardened Static Latch. M Omana, D Rossi, C Metra ITC, 886-892, 2003 | 99 | 2003 |
| Modeling and detection of hotspot in shaded photovoltaic cells D Rossi, M Omaña, D Giaffreda, C Metra IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (6 …, 2014 | 82 | 2014 |
| On transistor level gate sizing for increased robustness to transient faults JM Cazeaux, D Rossi, M Omaña, C Metra, A Chatterjee 11th IEEE International On-Line Testing Symposium, 23-28, 2005 | 65 | 2005 |
| Low cost NBTI degradation detection and masking approaches M Omaña, D Rossi, N Bosio, C Metra IEEE Transactions on Computers 62 (3), 496-509, 2011 | 58 | 2011 |
| Impact of aging phenomena on soft error susceptibility D Rossi, M Omaña, C Metra, A Paccagnella 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 46 | 2011 |
| Accurate linear model for SET critical charge estimation D Rossi, JM Cazeaux, M Omana, C Metra, A Chatterjee IEEE transactions on very large scale integration (VLSI) systems 17 (8 …, 2009 | 43 | 2009 |
| Impact of bias temperature instability on soft error susceptibility D Rossi, M Omaña, C Metra, A Paccagnella IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 743-751, 2014 | 42 | 2014 |
| Model for thermal behavior of shaded photovoltaic cells under hot-spot condition D Giaffreda, M Omaña, D Rossi, C Metra 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 40 | 2011 |
| Low cost scheme for on-line clock skew compensation M Omana, D Rossi, C Metra 23rd IEEE VLSI Test Symposium (VTS'05), 90-95, 2005 | 29 | 2005 |
| Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic C Metra, D Rossi, M Omana, A Jas, R Galivanche 2008 13th European Test Symposium, 171-176, 2008 | 27 | 2008 |
| Self-checking monitor for NBTI due degradation M Omaña, D Rossi, N Bosio, C Metra 2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test …, 2010 | 26 | 2010 |
| Fast and low-cost clock deskew buffer M Omana, D Rossi, C Metra 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2004 | 22 | 2004 |
| Model for transient fault susceptibility of combinational circuits M Omana, D Rossi, C Metra Journal of Electronic Testing 20, 501-509, 2004 | 19 | 2004 |
| High speed and highly testable parallel two-rail code checker M Omana, D Rossi, C Metra 2003 Design, Automation and Test in Europe Conference and Exhibition, 608-613, 2003 | 19 | 2003 |
| New design for testability approach for clock fault testing C Metra, M Omana, TM Mak, S Tam IEEE Transactions on Computers 61 (4), 448-457, 2011 | 18 | 2011 |
| Low cost and high speed embedded two-rail code checker M Omana, D Rossi, C Metra IEEE Transactions on Computers 54 (2), 153-164, 2005 | 18 | 2005 |
