| An efficient single precision floating point multiplier architecture based on classical recoding algorithm JJJ Nesam, S Sathasivam Indian Journal of Science and Technology, 2016 | 8 | 2016 |
| FPGA Based SCA Resistant AES S-Box Design SS Ganesh, JJJ Nesam International Journal of Scientific and Engineering Research, volume4, 2013 | 5 | 2013 |
| Efficient half-precision floating point multiplier targeting color space conversion JJJ Nesam, S Sivanantham Multimedia Tools and Applications 79 (1), 89-117, 2020 | 4 | 2020 |
| An area-efficient 32-bit floating point multiplier using hybrid GPPs addition JJJ Nesam, S Sivanantham 2017 International conference on Microelectronic Devices, Circuits and …, 2017 | 3 | 2017 |
| High speed half-precision floating-point fused multiply and add unit using DSP blocks SS Ganesh, JJJ Nesam, U Subramaniam 2020 First International Conference of Smart Systems and Emerging …, 2020 | 2 | 2020 |
| Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder JJJ Nesam, SS Ganesh Circuits, Systems, and Signal Processing 40 (4), 1832-1851, 2021 | 1 | 2021 |
| Reconfigurable half-precision floating-point real/complex fused multiply and add unit JJJ Nesam, S Sivanantham International Journal of Materials and Product Technology 60 (1), 58-72, 2020 | 1 | 2020 |
| Fully Pipelined High Speed SB and MC of AES Based on FPGA SS Ganesh, JJJ Nesam International Journal of Engineering and Technology (IJET), ISSN, 0975-4024, 0 | 1 | |
| RGB-to-Grayscale Conversion Using Truncated Floating-Point Multiplier SS Ganesh, JJJ Nesam Futuristic Communication and Network Technologies: Select Proceedings of …, 2023 | | 2023 |
| SINGLE CHIP IMPLEMENTATION OF MASKED AES WITH QPSK MODULATION FOR LONG DISTANCE TRANSMISSION SS Ganesh, JJJ Nesam | | |
