| Low power reconfigurable FP-FFT core with an array of folded DA butterflies ASB Paul, S Raju, R Janakiraman EURASIP journal on advances in signal processing 2014 (1), 144, 2014 | 16 | 2014 |
| Lifting-based discrete wavelet transform for real-time signal detection PH Anilkumar, PAS Beulet Indian Journal of Science and Technology 8 (25), 2015 | 12 | 2015 |
| Analysis and design of low power radix-4 FFT processor using pipelined architecture PA Sophy, R Srinivasan, J Raja, M Avinash Computing and Communications Technologies (ICCCT), 2015 International …, 2015 | 12 | 2015 |
| Implementation of a 32–bit RISC processor with floating point unit in FPGA platform S Sushma, SK Ravindran, PR Nadagoudar, PA Sophy Journal of Physics: Conference Series 1716 (1), 012047, 2020 | 4 | 2020 |
| Design and Implementation of Low-Power, Area-Efficient FIR Filter using Different Distributed Arithmetic Techniques P Ramesh, PAS Beulet Indian Journal of Science and Technology, 2015 | 3 | 2015 |
| Prediction of Jowar Crop Yield Using K-Nearest Neighbor and Support Vector Machine Algorithms S Pavani, P Augusta Sophy Beulet International Conference on Futuristic Communication and Network …, 2020 | 2 | 2020 |
| Low power implementation of a RISC machine using clock gating technique M Agarwal, R Pathak, P Sophy Proceedings of International Conference on Sustainable Computing in Science …, 2019 | 2 | 2019 |
| VLSI Design: Circuits, Systems and Applications: Select Proceedings of ICNETS2, Volume V J Li, AR Sankar, PAS Beulet Springer Singapore, 2018 | 2 | 2018 |
| Variable Length Floating Point FFT Processor Using Radix-2 Butterfly Elements PA Sophy, R Srinivasan, J Raja, SA Ganesh International Journal of Engineering and Technology (IJET) 6 (2), 2014 | 2 | 2014 |
| Implementation of Radix-2 Butterfly Using Distributed Arithmetic Algorithm (DAA) K Tarkas, C Sharma, O Mehta, P Augusta Sophy Beulet VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 1 | 2018 |
| An efficient hardware realization of distributed arithmetic based discrete cosine transform MS Rajeev, PAS Beulet Indian Journal of Science and Technology 8 (25), 2015 | 1 | 2015 |
| Radix-2 pipelined FFT processor with Gauss Complex multiplication method and vedic multiplier V Bogireddy, PA Sophy International Journal of Engineering Research and Technology 4, 2015 | 1 | 2015 |
| FPGA Implementation of 32 point Radix-2 Pipelined FFT A Arya, A Sophy International Journal of Research in Electronics & Communication Technology …, 2013 | 1 | 2013 |
| Single-Precision Floating-Point Addition Under HUB NS Sathyavathi, P Augusta Sophy Beulet International Conference on Futuristic Communication and Network …, 2020 | | 2020 |
| Design of Sample and Hold for High-Speed Analog to Digital Converter D Patel Konarkkumar, P Augusta Sophy Beulet VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | | 2018 |
| Design of Five Stage Pipelined Microprocessor with a 16K Cache Memory AA George, S Sadasivan, A Sophy International Journal of Applied Engineering Research 12 (10), 2294-2300, 2017 | | 2017 |
| Architectural framework for low power variable length FFT processor P Augusta Sophy Beulet Chennai, 0 | | |
| Variable Length Floating Point FFT Processor Using Radix-2 2 PA Sophy | | |
Ravi Sankar AVellore Institute of Technology (VIT), ChennaiVerified email at vit.ac.in
Ravi Sankar AVellore Institute of Technology (VIT), ChennaiVerified email at vit.ac.in