| Visual inertial odometry at the edge: A hardware-software co-design approach for ultra-low latency and power DK Mandal, S Jandhyala, OJ Omer, GS Kalsi, B George, G Neela, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 960-963, 2019 | 15 | 2019 |
| Logic-on-logic partitioning techniques for 3-dimensional integrated circuits G Neela, J Draper 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 789-792, 2013 | 13 | 2013 |
| Scalable memory-optimized hardware for matrix-solve GS Kalsi, OJ Omer, DK Mandal, SK Rethinagiri, G Neela US Patent 10,324,689, 2019 | 12 | 2019 |
| Challenges in 3DIC Implementation of a Design Using Current CAD Tools G Neela, J Draper | 8 | 2012 |
| Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC G Neela, J Draper 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013 | 6 | 2013 |
| Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture H Thapliyal, N Gopi, KKP Kumar, MB Srinivas IEEE International Conference on Computer Systems and Applications, 2006., 88-92, 2006 | 6 | 2006 |
| Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC G Neela, J Draper 2015 International 3D Systems Integration Conference (3DIC), TS8. 23.1-TS8. 23.6, 2015 | 5 | 2015 |
| An asymmetric adaptive-precision energy-efficient 3DIC multiplier G Neela, J Draper Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 5 | 2013 |
| A multi-mode energy-efficient double-precision floating-point multiplier G Neela, J Draper 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 3 | 2014 |
| Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC G Neela, J Draper 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 802-805, 2014 | 3 | 2014 |
| Modeling the Impact of TSVs on Average Wire Length in 3DICs using a Tier-Level Hierarchical Approach G Neela, J Draper 2014 IEEE Computer Society Annual Symposium on VLSI, 154-159, 2014 | 2 | 2014 |
| Optimized image feature extraction GS Kalsi, OJ Omer, B George, G Neela, DK Mandal, S Subramoney US Patent 10,318,834, 2019 | 1 | 2019 |
| Architecture to generate binary descriptor for image feature point G Neela, DK Mandal, GS Kalsi, P Laddha, OJ Omer, A Thyagharajan, ... US Patent 11,189,000, 2021 | | 2021 |
| A Logic Partitioning Framework and Implementation Optimizations for 3-Dimensional Integrated Circuits G Neela University of Southern California, 2015 | | 2015 |
