| Motion estimation method for video compression-an overview M Manikandan, P Vijayakumar, N Ramadass 2006 IFIP International Conference on Wireless and Optical Communications …, 2006 | 24 | 2006 |
| Heading control of ROV ROSUB6000 using non-linear model-aided PD approach R Ramesh, N Ramadass, D Sathianarayanan, N Vedachalam, ... International Journal of Emerging Technology and Advanced Engineering 3 (4 …, 2013 | 21 | 2013 |
| Low cost home automation using offline speech recognition G Prasanna, N Ramadass International Journal of Signal Processing Systems 2 (2), 96-101, 2014 | 12 | 2014 |
| An adaptive symbiosis based metaheuristics for combinatorial optimization in VLSI LL Laudis, N Ramadass, S Shyam, R Benschwartz, V Suresh Procedia Computer Science 167, 205-212, 2020 | 7 | 2020 |
| A Lion’s pride inspired algorithm for VLSI floorplanning LL Laudis, N Ramadass Journal of Circuits, Systems and Computers 29 (01), 2050003, 2020 | 3 | 2020 |
| State-based dynamic multi-alphabet arithmetic coding for image compression S Natarajan, N Ramadass, RYV Rao The Imaging Science Journal 57 (1), 30-36, 2009 | 3 | 2009 |
| Dynamically reconfigurable embedded architecture an alternative to application specific digital signal processing architectures N Ramadass, S Natarajan, JRP Perinbam Journal of computer science, 832-828, 2007 | 2 | 2007 |
| A Novel Architecture For Modified Algebraic Code Book Search N Ramadass, GMA Ibrahim, S Natarajan, JRP Perinbam Proceedings of the International Conference Mixed Design of Integrated …, 2006 | 2 | 2006 |
| Self-Modifiable Mixed-Signal SoC Architecture for Embedded Applications S Natarajan, N Ramadass National Conference on Signals, Systems and Communications (NCSSC 2005 …, 2005 | 2 | 2005 |
| Totally self-checking (TSC) VLSI circuits using Scalable Error Detection Coding (SEDC) technique N Somasundaram, F Mehdipour, JA Lee, N Ramadass, YVR Rao Fifth Asia Symposium on Quality Electronic Design (ASQED 2013), 72-79, 2013 | 1 | 2013 |
| Scalable Error Detection Coding© Algorithm for Totally Self-Checking (TSC) Circuits SEDC© Algorithm for TSC Circuits N Somasundaram, JA Lee, F Mehdipour, R Narayanadass, YVR Rao Consumer Electronics Times, 2013 | 1 | 2013 |
| Dynamically Reconfigurable (Self-modifiable) Architecture for Embedded System-on-Chip Applications N Ramadass, S Natarajan, JRP Perinbam Information Technology Journal. 6, 66, 2007 | 1 | 2007 |
| Power reduction using Unified techniques in Switch-tail Ring counter for sequential circuits L Angel Prabha, N Ramadass Analog Integrated Circuits and Signal Processing 119 (1), 131-149, 2024 | | 2024 |
| High Efficient Reconfigurable and Self Testable Architecture for Sensor Node. G Venkatesan, N Ramadass Computer Systems Science & Engineering 46 (3), 2023 | | 2023 |
| A Systematic Review and Research of Energy Efficient Evaluation in WSNs. G Venkatesan, N Ramadass Turkish Online Journal of Qualitative Inquiry 12 (6), 2021 | | 2021 |
| Development of Combinational Circuits by Encoding on the Basis of Developmental Biology SBSRSN Ramadass Computational Intelligence and Neuroscience 2020 (Article ID 7696398), 14, 2020 | | 2020 |
| Design of a High Speed and Low Power Analog to Digital Converter P Venugopal, V Ranganathan, N Ramadass Journal of Computational and Theoretical Nanoscience 14 (3), 1521-1523, 2017 | | 2017 |
| An Efficient Algorithm With Low Power Implementation For Hearing Aids L Joseph Jeyakumar, D, Raja Paul Perinbam,J,Ramadass,N, Vinoth International Journal of Applied Engineering Research (IJAER) 10 (11, ISSN …, 2015 | | 2015 |
| Real Time Face Recognition Based on PCA and Artificial Neural Network DNR P.Priyadharshini International Journal of Applied Engineering Research (IJAER) 10 (Number 22 …, 2015 | | 2015 |
| Dynamically reconfigurable bit parallel pipelined embedded architecture for high speed signal processing N Ramadass Chennai, 2008 | | 2008 |
Dr.Natarajan SomasundaramAssociate Professor, Department of Computer Science and Engineering, Amrita Vishwa VidyapeethamVerified email at ch.amrita.edu
